Patent application number | Description | Published |
20090079061 | THERMALLY ENHANCED ELECTRONIC FLIP-CHIP PACKAGING WITH EXTERNAL-CONNECTOR-SIDE DIE AND METHOD - A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One or more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole. | 03-26-2009 |
20100309704 | In-pakage microelectronic apparatus, and methods of using same - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 12-09-2010 |
20110147055 | Glass core substrate for integrated circuit devices and methods of making the same - Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed. | 06-23-2011 |
20110147929 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 06-23-2011 |
20110156283 | Use of die backside films to modulate EOL coplanarity of thin packages while providing thermal capability and laser markability of packages - A microelectronic package comprises a die ( | 06-30-2011 |
20110241215 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 10-06-2011 |
20120077357 | SELF REFERENCING PIN - Methods and apparatus relating to self-referencing pins are described. In one embodiment, a pin electrically couples a first agent to a second agent. The pin includes two or more portions that are at least partially separated by an insulator, e.g., to improve crosstalk performance. Other embodiments are also disclosed and claimed. | 03-29-2012 |
20120112336 | ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE - An encapsulated die ( | 05-10-2012 |
20120113704 | IN-PACKAGE MICROELECTRONIC APPARATUS, AND METHODS OF USING SAME - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 05-10-2012 |
20120192413 | GLASS CORE SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES AND METHODS OF MAKING THE SAME - Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed. | 08-02-2012 |
20120299179 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be farmed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 11-29-2012 |
20130270715 | PACKAGED SEMICONDUCTOR DIE WITH BUMPLESS DIE-PACKAGE INTERFACE FOR BUMPLESS BUILD-UP LAYER (BBUL) PACKAGES - A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. | 10-17-2013 |
20130328207 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 12-12-2013 |
20140024174 | USING AN OPTICALLY TRANSPARENT SOLID MATERIAL AS A SUPPORT STRUCTURE FOR ATTACHMENT OF A SEMICONDUCTOR MATERIAL TO A SUBSTRATE - Electronic devices and methods for fabricating electronic devices are described. One method includes attaching an optically transparent solid material to a body of semiconducting material in which microelectronic devices are formed. The method also includes attaching a first surface of a body portion, comprising a portion of the body, to a substrate while a portion of the optically transparent solid material is attached to a second surface of the body portion. The method also includes removing the optically transparent solid material from the second surface of the body portion after the attaching the first surface of the body portion to the substrate. | 01-23-2014 |
20140085846 | MICROELECTRONIC STRUCTURES HAVING LAMINATED OR EMBEDDED GLASS ROUTING STRUCTURES FOR HIGH DENSITY PACKAGING - Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure. | 03-27-2014 |
20140152383 | INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR PRODUCING THE SAME - Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described. | 06-05-2014 |
20140167900 | SURFACE-MOUNT INDUCTOR STRUCTURES FOR FORMING ONE OR MORE INDUCTORS WITH SUBSTRATE TRACES - Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed. | 06-19-2014 |
20140169801 | SEMICONDUCTOR PACKAGE WITH OPTICAL PORT - Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described. | 06-19-2014 |
20140171751 | ELECTRONIC BIO MONITORING PATCH - Described herein are technologies related to a wireless electronic vital sign monitoring of a person. More particularly, detecting vital signs and processing of the detected vital signs using a bio monitoring patch. | 06-19-2014 |
20140175643 | APPARATUSES AND METHODS TO ENHANCE PASSIVATION AND ILD RELIABILITY - Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices. | 06-26-2014 |
20140176417 | WEARABLE PROJECTOR FOR PORTABLE DISPLAY - Described herein are technologies related to a wearable projector to project images, information, multimedia, etc. in a portable display. More particularly, the wearable projector includes a system on chip (SOC) microprocessor that is configured to project the images, information, multimedia, etc. to different types of portable display such as, flexible transparent plastic, glass, paper, and the like. | 06-26-2014 |
20140178003 | CLOAKING SYSTEM WITH WAVEGUIDES - Described herein are technologies related to passive or active cloaking devices. More particularly, the passive or active cloaking devices utilize input/output grating couplers and waveguides to create an impression of invisibility on an object that is covered by the passive or active cloaking devices. | 06-26-2014 |
20140203379 | INTEGRATION OF LAMINATE MEMS IN BBUL CORELESS PACKAGE - An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed. | 07-24-2014 |
20140217579 | HIGH DENSITY PACKAGE INTERCONNECTS - Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. | 08-07-2014 |
20140217585 | 3D INTEGRATED CIRCUIT PACKAGE WITH THROUGH-MOLD FIRST LEVEL INTERCONNECTS - 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die. | 08-07-2014 |
20140264910 | INTERCONNECT STRUCTURES WITH POLYMER CORE - Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed. | 09-18-2014 |
20150084210 | HIGH DENSITY SUBSTRATE INTERCONNECT USING INKJET PRINTING - Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge. | 03-26-2015 |