Patent application number | Description | Published |
20080286933 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 11-20-2008 |
20090033368 | LOGIC BLOCK, A MULTI-TRACK STANDARD CELL LIBRARY, A METHOD OF DESIGNING A LOGIC BLOCK AND AN ASIC EMPLOYING THE LOGIC BLOCK - A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height. | 02-05-2009 |
20090160029 | Scribe Seal Structure for Improved Noise Isolation - Disclosed is a semiconductor wafer with an array of integrated circuit chips with scribe lane structures forming edge and intra-chip seals for use in protecting the IC circuitry. Substantially parallel scribe seal structures extend around the periphery of each chip; the two scribe seal structures have a separation gap. Preferred embodiments of the invention also include wafers of ICs each having two or more distinctive circuitry blocks such as analog and digital circuitry, separated by an intra-chip seal. Preferred embodiments of also include ICs having two or more distinctive circuit blocks separated by a scribe seal structure with a separation gap and a routing channel for use in passing signals among the circuit blocks. | 06-25-2009 |
20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 04-29-2010 |
20110133880 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 06-09-2011 |
20110216619 | MEMORY POWER MANAGEMENT SYSTEMS AND METHODS - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 09-08-2011 |
20120102441 | MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS - A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site. | 04-26-2012 |
20120286331 | INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS - Integrated circuit ( | 11-15-2012 |