Patent application number | Description | Published |
20080229078 | Dynamic Power Management in a Processor Design - Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power. | 09-18-2008 |
20080256345 | Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System - An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions. | 10-16-2008 |
20090043997 | Time-Of-Life Counter For Handling Instruction Flushes From A Queue - Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values. | 02-12-2009 |
20090063818 | Alignment of Cache Fetch Return Data Relative to a Thread - A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first sector in at least one alignment register, thereby permitting the at least first sector to be bypassed. | 03-05-2009 |
20090150657 | Method and Apparatus for Inhibiting Fetch Throttling When a Processor Encounters a Low Confidence Branch Instruction in an Information Handling System - An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. | 06-11-2009 |
20090177858 | Method and Apparatus for Controlling Memory Array Gating when a Processor Executes a Low Confidence Branch Instruction in an Information Handling System - An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely. | 07-09-2009 |
20090193231 | METHOD AND APPARATUS FOR THREAD PRIORITY CONTROL IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible. | 07-30-2009 |
20090193240 | METHOD AND APPARATUS FOR INCREASING THREAD PRIORITY IN RESPONSE TO FLUSH INFORMATION IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction. In this manner, a fetcher in the processor obtains ready access to the particular thread in the memory array. | 07-30-2009 |