Patent application number | Description | Published |
20080206914 | Patterning self-aligned transistors using back surface illumination - Fabrication methods for making thin film devices on transparent substrates are described. Gate, source, and drain electrodes of a transistor are formed on a transparent substrate. The widths of the drain electrode and source electrodes are greater than a width of the gate electrode. A dielectric layer is formed on the gate electrode. A semiconductor layer is deposited proximate to the gate, source and drain electrodes. Photoresist is deposited on the semiconductor. The photoresist is exposed to light directed through the transparent substrate so that the gate electrode masks the photoresist from the light. The semiconductor layer is removed in regions exposed to the light. | 08-28-2008 |
20090159886 | PRINTED TFT ARRAY - An electronic device and/or component is manufactured using additive processing steps, including additive printing steps. A first layer is printed using additive printing techniques wherein a single first material is used to print the first layer in a single processing step. A second layer is printed in more than a single printing step where a first portion of the second layer is printed using a second material and a second portion of the second layer is printed using a third material, and the second and third materials are different from each other. | 06-25-2009 |
20090159971 | PRINTED TFT AND TFT ARRAY WITH SELF-ALIGNED GATE - A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact. | 06-25-2009 |
20090161409 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 06-25-2009 |
20090184954 | DESIGN AND ADDRESSING OF A THREE-DIMENSIONAL, CURVED SENSOR OR DISPLAY BACK PLANE - A method of forming a three-dimensional electronic device includes forming an array of pixels on a flexible two-dimensional surface, the array being formed according to a three-dimensional structure, the pixels having addressing lines accessible from at least one edge of the array, cutting the two-dimensional surface, the cuts being located to allow the two-dimensional surface to be shaped, and shaping the two-dimensional surface to form the three-dimensional surface, the array of pixels forming the three-dimensional electronic device. A three-dimensional electronic device has a flexible substrate containing an array of pixels, the substrate fabricated as a flat surface, then cut and shaped to form a three-dimensional surface, the array of pixels covering the three-dimensional surface in subarrays corresponding to segments of the three-dimensional surface, and addressing lines for each subarray being accessible along an edge of the three-dimensional surface. A method of forming a three-dimensional electronic device includes providing a flexible substrate, forming address lines on the substrate such that the address lines are accessible at an edge of the substrate, forming pixels on the address lines, the pixels being laid out in subarrays, the subarrays being determined by segments of a three-dimensional surface, and accommodating any cuts that will allow the flexible substrate to form the three-dimensional electronic device in the forming of addressing lines and pixels. | 07-23-2009 |
20100060560 | LARGE AREA ELECTRONIC SHEET AND PIXEL CIRCUITS WITH DISORDERED SEMICONDUCTORS FOR SENSOR ACTUATOR INTERFACE - A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same. | 03-11-2010 |
20100067280 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100067316 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100068856 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 03-18-2010 |
20100096729 | GEOMETRY AND DESIGN FOR CONFORMAL ELECTRONICS - A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions. | 04-22-2010 |
20100099220 | ELECTRONIC DEVICE WITH UNIQUE ENCODING - An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2 | 04-22-2010 |
20100181871 | SENSORS AND ACTUATORS USING PIEZO POLYMER LAYERS - A device has a substrate, a piezo polymer layer arranged adjacent the substrate, a first electrode in contact with a first side of the layer, and a second electrode arranged adjacent the first electrode, such that when the piezo layer flexes, the first and second electrodes are arranged to detect one of a change in voltage or resistance, wherein at least one of the piezo polymer layer or the electrodes are deposited by printing. A method including depositing a spacer layer onto a substrate, depositing a piezo polymer layer onto the substrate, patterning an array of first electrodes in contact with the piezo polymer layer, and patterning an array of second electrodes adjacent the array of first electrodes, wherein depositing includes one of printing and laminating and pattering includes one of printing and etching. A method including laminating a piezo polymer layer onto a substrate, such that the layer forms at least one cantilever beam, forming a first electrode on one side of the layer, arranging a second electrode adjacent the first electrode, printing a polymer layer on the cantilever beam, and printing a proof mass on the cantilever beam. | 07-22-2010 |
20100201612 | PHOTORECEPTOR WITH A TFT BACKPLANE FOR XEROGRAPHY WITHOUT A ROS SYSTEM - Systems and methods are described that facilitate eliminating a need for a raster output scanner (ROS) or laser when generating a latent image on a photoreceptor. An addressable backplane is employed, comprising an array of field effect transistors (e.g., silicon or organic thin film transistors, or TFTs), wherein each TFT corresponds to a single pixel on a charge transport layer on the photoreceptor surface. Latent image formation is performed by forming a surface potential using corona charging, and then directing free charge carriers toward the photoreceptor surface to reduce electrostatic potential in areas that need to be toned. TFTs in the array are individually addressed, or selected, to connect to a common ground, which allows photodischarge to occur only in selected areas (e.g., pixels associated with the selected TFTs). Once the array of TFTs is addressed, an LED light source emits light over the surface of the photoreceptor, and only the selected (grounded) TFTs permit their associated pixels to discharge. In this manner, a latent image is formed without a need for a bulky and expensive ROS. | 08-12-2010 |
20100201777 | IMAGE FORMING APPARATUS WITH A TFT BACKPLANE FOR XEROGRAPHY WITHOUT A LIGHT SOURCE - Systems and methods are described that facilitate using TFT control of electronic discharge for surface potential reduction and latent image formation on an imaging member. Corona charging is performed to first create a background surface potential, followed by selective discharge of individual pixels using an array of TFTs to supply free charge carriers to reduce the electrostatic surface potential to nearly zero. This is followed by discharged area development (DAD) to develop the latent image on a print medium (e.g., paper). The described systems and methods do not require a HVPS to drive the backplane; therefore, the TFT matrix is electrostatically decoupled from the developer and other system components in direct contact with the imaging member. Accordingly, known addressing systems may be used to address the TFT array. | 08-12-2010 |
20100317159 | Vertical Coffee-Stain Method For Forming Self-Organized Line Structures - A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 12-16-2010 |
20100317160 | HORIZONTAL COFFEE-STAIN METHOD USING CONTROL STRUCTURE TO PATTERN SELF-ORGANIZED LINE STRUCTURES - A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 12-16-2010 |
20110027946 | Horizontal Coffee-Stain Method Using Control Structure To Pattern Self-Organized Line Structures - A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 02-03-2011 |
20110068999 | SHAPED ACTIVE MATRIX DISPLAYS - A display system has an array of display elements on a substrate arranged into a shape having a non-rectangular perimeter, and address lines arranged to transmit signals to the display elements, the address lines conforming at least partially to the non-rectangular perimeter. A display system has an array of display elements arranged on a substrate, the substrate having at least one holes, and address lines arranged on the substrate to address the display elements, the address lines being routed according to the hole. A method of manufacturing a display system includes providing a substrate having a curved perimeter, mapping a rectangular addressing matrix to a curved matrix, the curved matrix based on the curved perimeter, forming address lines according to the curved matrix such that the address lines converge on at least one point, providing an array of display elements arranged to be addressable by the address lines, and providing control circuitry at the point to provide signals to the display elements through the address lines. A method of manufacturing a display system includes providing a substrate, arranging address lines on the substrate, such that the address lines are routed to avoid at least one region on the substrate, forming a hole in the region, wherein the hole penetrates at least partially into the substrate, and providing display elements on the substrate, arranged to be addressable by the address lines. | 03-24-2011 |
20110083728 | Disordered Nanowire Solar Cell - A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible. | 04-14-2011 |
20110095272 | Organic Memory Array With Ferroelectric Field-Effect Transistor Pixels - An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data. | 04-28-2011 |
20110141476 | LIGHT SCATTERING MEASUREMENT SYSTEM BASED ON FLEXIBLE SENSOR ARRAY - A compact, optical measurement system has a non-flat detector array having multiple detector elements arranged on a flexible substrate in a monolithic fashion, one or more illumination sources arranged to provide more than one angle of incidence of light on a subject being measured, and a detection system in electrical communication with the detector array, the detection system arranged to receive inputs from the detector array and provide a measurement from the inputs. A method of measuring reflectance of a surface includes placing the surface adjacent a hemispherical detector array, illuminating the surface from a predetermined angle of incidence, simultaneously detecting reflectance at multiple emission angles using the hemispherical detector array, and repeating the illuminating and detecting processes at different angles of incidence. Optional arrays of lenses, baffles and filters may be employed by the system. | 06-16-2011 |
20110185322 | METHOD OF IN-PROCESS INTRALAYER YIELD DETECTION, INTERLAYER SHUNT DETECTION AND CORRECTION - A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects. | 07-28-2011 |
20110290296 | FLEXIBLE TILED PHOTOVOLTAIC MODULE - A flexible photovoltaic module has a flexible substrate having integrated electrically conductive portions, an array of functional tiles on the substrate, wherein the functional tiles include solar cell tiles, the functional tiles being separated by a spacing which determines the bending radius of the module, the tiles at least partially in electrical contact with the electrically conductive portions, the solar tiles electrically connected in one of either electrical series or parallel configuration to produce an electrical power output. A method of manufacturing flexible, photovoltaic modules, includes manufacturing at least one functional material, forming the functional material into functional tiles, mounting the functional tiles onto a flexible substrate into an array of functional tiles with spacing between the tiles, the spacing selected to provide flexibility, and forming circuitry on the flexible substrate to electrically connect the functional tiles to one of either input/output circuitry or other tiles. | 12-01-2011 |
20120031396 | Luminescent Solar Concentrator With Distributed Outcoupling Structures And Microoptical Elements - A luminescent solar concentrator including a light-guiding slab containing a luminescent material that generates light emissions in response to received sunlight, spaced-apart outcoupling structures that provide a distributed outcoupling of the light emissions through predetermined locations on one of the “broadside” (e.g., upper or lower) surfaces of the light-guiding slab, and optical elements positioned to redirect the outcoupled light emissions such that the light emissions are concentrated onto a predetermined target (e.g., a PV cell). Each optical element includes a collimating surface portion and optional returner surface. | 02-09-2012 |
20120031467 | Solar Energy Harvesting System Using Luminescent Solar Concentrator With Distributed Outcoupling Structures And Microoptical Elements - A solar energy harvesting system including a luminescent solar concentrator for generating light emissions in response to received sunlight, and for redirecting and concentrating the light emissions onto a predetermined target (e.g., a PV cell). The luminescent solar concentrator includes a light-guiding slab containing a luminescent material that generates the light emissions, spaced-apart outcoupling structures that provide a distributed outcoupling of the light emissions through predetermined locations on one of the “broadside” (e.g., upper or lower) surfaces of the light-guiding slab, and optical elements positioned to redirect the outcoupled light emissions such that the light emissions are concentrated onto the predetermined target. | 02-09-2012 |
20120037992 | PRINTED TFT AND TFT ARRAY WITH SELF-ALIGNED GATE - A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact. | 02-16-2012 |
20120164781 | Disordered Nanowire Solar Cell - A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible. | 06-28-2012 |
20130001689 | TEXTURED GATE FOR HIGH CURRENT THIN FILM TRANSISTORS - A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current. | 01-03-2013 |
20130115846 | SELF ASSEMBLY OF FIELD EMISSION TIPS BY CAPILLARY BRIDGE FORMATIONS - A first side has a first surface on which is located a material, at least a portion of which is to be formed into at least one tip. A second side has a second surface which is heated. At least one of the first and second surfaces being moved so material located on the first surface comes into physical contact with the second surface. Then at least one of the first side and the second side are moved, wherein the physical contact between the material and the second surface is maintained, causing the material to stretch between the second surface and the first surface, generating at least one capillary bridge. Movement is continued until the physical contact between the material and the second surface is broken resulting in the formation of at least one sharp conductive tip. | 05-09-2013 |
20130157447 | SINGLE CRYSTAL SILICON TFTS MADE BY LATERAL CRYSTALLIZATION FROM A NANOWIRE SEED - A method can include depositing a thin metal film on a substrate of a sample, establishing a metal island on the substrate by patterning the thin metal film, and annealing the sample to de-wet the metal island and form a metal droplet from the metal island. The method can also include growing a nanowire on the substrate using the metal droplet as a catalyst, depositing a thin film of a semiconductor material on the sample, annealing the sample to allow for lateral crystallization to form a crystal grain, and patterning the crystal grain to establish a crystal island. An electronic device can be fabricated using the crystal island. | 06-20-2013 |
20140000108 | GEOMETRY AND DESIGN FOR CONFORMAL ELECTRONICS | 01-02-2014 |
20140041504 | Mechanical Method For Producing Micro- Or Nano-Scale Textures - A mechanical method for producing micro-scale and nano-scale textures that facilitates, for example, the cost-effective production of nanostructures on large-scale substrates, e.g., during the large-scale production of thin-film solar cells. A “scratcher” (multi-pointed abrasion mechanism) is maintained in a precise position relative to a target substrate such that micron-level features (protrusions) extending from the scratcher's base structure are precisely positioned to contact a surface material layer of the target substrate with a predetermined amount of force, and then moved relative to the substrate (e.g., by way of a conveying mechanism) while maintaining the pressing force such that the micron-level features define elongated parallel nano-scale grooves and/or form nano-scale ridges in the surface material layer (i.e., by mechanically displacing) portions of the surface material layer to form the nano-scale grooves/ridges). | 02-13-2014 |
20140264436 | SOLUTION PROCESSED NEUTRON DETECTOR - A low-cost neutron detector is formed on a substrate includes a sensor formed by an active material layer sandwiched between two electrodes, and a neutron capture layer formed in close proximity to (i.e., over and/or under) the sensor. The sensor active material layer includes a bulk heterojunction or bilayer structure that is formed by depositing particulate solutions incorporating at least one type of high atomic number nanoparticle using low-temperature (i.e., below 400° C.) solution processing techniques. The sensor electrode material and neutron capture material are similarly disposed in associated solutions (e.g., conductive inks) that are also deposited using low-temperature solution processing techniques, whereby the fabrication process can be carried out on low-cost flexible substrate material (e.g., PET) using high efficiency roll-to-roll production techniques. The neutron capture material is optionally patterned as an array of pillars, and the active layer materials are backfilled between the pillars. | 09-18-2014 |