| Patent application number | Description | Published |
|---|
| 20090154274 | Memory Read Stability Using Selective Precharge - A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground. | 06-18-2009 |
| 20090160253 | System and Method of Providing Power Using Switching Circuits - In a particular illustrative embodiment, a system is disclosed that includes a first power domain that is responsive to a first power switching circuit and a second power domain that is responsive to a second power switching circuit. The system also includes a logic circuit adapted to selectively activate the first power switching circuit and the second power switching circuit. At least one of the first power switching circuit and the second power switching circuit includes a first set of transistors adapted for activation during a first power up stage and a second set of transistors adapted for activation during a second power up stage after at least one of the first set of transistors are activated. | 06-25-2009 |
| 20090195268 | Level Shifting Circuit and Method - In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level shifting circuit. | 08-06-2009 |
| 20100046276 | Systems and Methods for Handling Negative Bias Temperature Instability Stress in Memory Bitcells - A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one embodiment, the trigger event is an alternate memory power-up. | 02-25-2010 |
| 20100052763 | CMOS Level Shifter Circuit Design - A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled between the input and output points. Each assist circuit includes a pair of PMOS transistors, one responsive to an input applied to the input point, the other responsive to the drain voltage of one of the NMOS transistors. The assist circuits temporarily weaken the cross-coupled PMOS transistors when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output. | 03-04-2010 |
| 20100103755 | Read Assist for Memory Circuits - A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage. | 04-29-2010 |
| 20100195366 | Reducing Leakage Current in a Memory Device - Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch. | 08-05-2010 |
