Patent application number | Description | Published |
20080253059 | LAND GRID FEEDTHROUGH LOW ESL TECHNOLOGY - Disclosed are apparatus and methodology for providing land grid feedthrough capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Low equivalent series inductance (ESL) is provided by current cancellation techniques involving opposite current flow in power or signal and ground current paths through the device. | 10-16-2008 |
20080310076 | CONTROLLED ESR DECOUPLING CAPACITOR - Disclosed are apparatus and methodology for providing controlled equivalent series resistance (ESR) decoupling capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Controlled equivalent series resistance (ESR) is provided by providing extended length tab connections to active electrode layers within the device. | 12-18-2008 |
20090002921 | MULTILAYER CERAMIC CAPACITOR WITH INTERNAL CURRENT CANCELLATION AND BOTTOM TERMINALS - Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface. | 01-01-2009 |
20090147440 | LOW INDUCTANCE, HIGH RATING CAPACITOR DEVICES - Methodologies and structures are disclosed for providing multilayer electronic devices having low inductance and high ratings, such as for capacitor devices for uses involving faster pulsing and higher currents. Plural layer devices are constructed for relatively lowered inductance by relatively altering typical orientation of capacitors such that their electrodes are placed into a vertical position relative to an associated circuit board. Optionally, individual leads may be formed so that the resulting structure can be used as an array. Internal electrodes may be arranged for reducing current loops for associated circuits on a circuit board, to correspondingly reduce the associated inductance of the circuit board mounted device. Leads associated with such devices may have added tab-like structures which serve to more precisely place the lead, to improve the lead to capacitor strength, and to promote lower resistance and inductance. Disclosed designs for reducing associated inductance may be practiced in conjunction with various electric devices, including capacitors, resistors, inductors, or varistors. | 06-11-2009 |
20100039749 | ULTRA BROADBAND CAPACITOR - Disclosed are apparatus and methodology for inexpensive realization of one or more secondary capacitors within a monolithic body that already includes a first, larger capacitor to provide ultra wideband structures. Alternating layers of electrodes are provided with arm portions that embrace portions of adjacent electrode layers so as to create additional coupling effects within the capacitor structure thereby producing multiple additional equivalent capacitor structures within the device. | 02-18-2010 |
20100188799 | CONTROLLED ESR LOW INDUCTANCE CAPACITOR - Multilayer capacitors incorporate both low inductance (ESL) and controlled Equivalent Series Resistance (ESR) features into a cost-effective unitary device. Internal electrode patterns generally include one or more pairs of mother electrodes adapted for external connection (e.g., to a circuit, another electrical component, circuit board, or other mounting environment), and multiple pairs of daughter electrodes adapted only for internal connection to other electrodes (e.g., other daughter electrodes and/or selected mother electrodes) without direct connection to an external circuit. Mother and daughter electrodes are interdigitated with electrode tab features, where daughter electrodes have internal-connection tabs, and mother electrodes have both internal-connection tabs and circuit-connection tabs, all of which are connected to respective internal-connection or circuit-connection terminals. ESR is increased by the parallel connection between mother and daughter electrodes as well as other optional features such as but not limited to resistive terminations, resistive connectors, serpentine terminations and increased current path lengths. | 07-29-2010 |
20110090665 | THIN FILM SURFACE MOUNT COMPONENTS - Surface mount components and related methods of manufacture involve one or more thin film circuits provided between first and second insulating substrates. The thin film circuits may include one or more passive components, including resistors, capacitors, inductors, arrays of one or more passive components, networks or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads being exposed between the substrates on end and/or side surfaces of the surface mount component. The exposed conductive pads are then electrically connected to external terminations. The external terminations may include a variety of different materials, including at least one layer of conductive polymer and may be formed as termination stripes, end caps or the like. Optional shield layers may also be provided on top and/or bottom device surfaces to protect the surface mount components from signal interference. For embodiments where one or more thin film circuits are provided between insulating base and cover substrates, such thin film circuit(s) can be formed with conductive pads that extend to and are initially exposed along one or more surfaces of the resultant component. The cover substrate is formed with a plurality of conductive elements (e.g., internal active electrodes, internal anchor electrodes and/or external anchor electrodes) that are designed to generally align with the conductive pads formed on the base substrate such that conductive element portions are exposed in groups along one or more peripheral surfaces of a device. External plated terminations are then formed directly to the exposed portions of the conductive elements. | 04-21-2011 |
Patent application number | Description | Published |
20130240366 | PLATED TERMINATIONS - Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. | 09-19-2013 |
20140062618 | ELECTROMAGNETIC INTERFERENCE FILTER FOR IMPLANTED ELECTRONICS - An electromagnetic interference filter for various electronic devices such as implantable medical devices is provided. A plurality of signal electrodes can be configured in an array, where each signal electrode extends vertically from a top surface to a bottom surface of the filter such that the signal electrodes are flush with the top and bottom surface. Ground or common electrodes can have a parallel arrangement and be interposed between the signal electrodes. The ground electrodes can be grounded internally, externally, or both internally and externally. Dielectric material can be disposed between signal electrodes and ground electrodes to act as an insulator between adjacent electrodes. | 03-06-2014 |
20140261606 | THERMOELECTRIC GENERATOR - Disclosed are apparatus and methodology for constructing thermoelectric devices (TEDs). N-type elements are paired with P-type elements in an array of pairs between substrates. The paired elements are electrically connected in series by various techniques including brazing for hot side and/or also cold side connections, and soldering for cold side connections while being thermally connected in parallel. In selected embodiments, electrical and mechanical connections of the elements may be made solely by mechanical pressure. | 09-18-2014 |
20140266002 | THERMOELECTRIC GENERATOR - Disclosed are apparatus and methodology for constructing thermoelectric devices (TEDs). N-type elements are paired with P-type elements in an array of pairs between substrates. The paired elements are electrically connected in series by various techniques including brazing for hot side and/or also cold side connections, and soldering for cold side connections while being thermally connected in parallel. In selected embodiments, electrical and mechanical connections of the elements may be made solely by mechanical pressure. | 09-18-2014 |