Patent application number | Description | Published |
20090166782 | WAFER PROCESSING - Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool. | 07-02-2009 |
20090231826 | Method of forming a permanent carrier and spacer wafer for wafer level optics and associated structure - A carrier wafer for wafer level fabrication of imager structures comprising a substrate with trenches corresponding to locations of imager arrays on an imager wafer. A method of fabricating such a carrier wafer and a method of fabricating an imager module employing such a carrier wafer are also provided. | 09-17-2009 |
20090261516 | METHOD AND APPARATUS FOR STEP-AND-REPEAT MOLDING - A method and apparatus for molding a structure on the top surface of a substrate. Mold material is dispensed onto an area of the top surface of the substrate. The mold apparatus is positioned over the area. The mold portion of the mold apparatus is positioned above the mold material and the mold material is surrounded with a shroud of the mold apparatus. A seal is formed between the shroud and the top surface of the substrate. The pressure is reduced within the shroud to below the ambient pressure. The mold portion of the mold apparatus is lowered toward the top surface of the substrate, so that at least the outer edge of the mold portion is in contact with the mold material. The pressure within the shroud is raised to at least the ambient pressure, and the mold material is cured to form the structure. | 10-22-2009 |
20100123209 | Apparatus and Method of Manufacture for Movable Lens on Transparent Substrate - A lens stack having a movable lens attached to a MEMS structure and method of fabricating the same. The method comprises attaching at least one MEMS structure to a transparent substrate. The method further comprises forming a movable lens in contact with the at least one MEMS structure. | 05-20-2010 |
20110233705 | WAFER PROCESSING - Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool. | 09-29-2011 |
20120186741 | APPARATUS FOR WAFER-TO-WAFER BONDING - An apparatus for bonding semiconductor wafers together including a moveable upper bond head and a resilient member positioned on a surface of the bond head for contacting a first wafer that is positioned at an elevation below the upper bond head. The resilient member is configured to apply a force onto a top side surface of the first wafer thereby compressing the first wafer against a second wafer that is positioned at an elevation below the first wafer. A method of wafer to wafer bonding includes the steps of positioning at least two wafers beneath the moveable upper bond head, positioning the resilient member in physical contact with one of the at least two wafers, and resiliently deforming the resilient member as it is moved into contact with the wafer to facilitate bonding of the wafers. | 07-26-2012 |
20140284375 | MICROFEATURE WORKPIECES HAVING ALLOYED CONDUCTIVE STRUCTURES, AND ASSOCIATED METHODS - Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2. | 09-25-2014 |
20150031171 | METHODS FOR FORMING CONDUCTIVE ELEMENTS AND VIAS ON SUBSTRATES AND FOR FORMING MULTI-CHIP MODULES - Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed. | 01-29-2015 |
Patent application number | Description | Published |
20080246066 | Optic wafer with reliefs, wafer assembly including same and methods of dicing wafer assembly - An optic wafer for assembly with an imager wafer, the optic wafer comprising a plurality of reliefs in a surface thereof coincident with street locations separating mutually adjacent optic element locations. A wafer assembly that includes the optic wafer and an imager wafer and methods of dicing a wafer assembly are also disclosed. | 10-09-2008 |
20080272466 | SEMICONDUCTOR SUBSTRATES INCLUDING VIAS OF NONUNIFORM CROSS SECTION AND ASSOCIATED STRUCTURES - Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the form of a hollow ball, extending laterally further within the wafer than the first portion. Backgrinding the wafer to the second portion of the via may create a vent. A conductive path may be formed by filling the via with a conductive material, such as solder. Flux gases may escape through the vent. The wafer surrounding the second portion of the via may be removed, exposing a conductive element in the shape of a ball, the shape of the second portion of the via. Semiconductor devices including the conductive paths of the present invention are also disclosed. | 11-06-2008 |
20080272497 | METHODS OF FORMING CONDUCTIVE VIAS THROUGH SUBSTRATES, AND STRUCTURES AND ASSEMBLIES RESULTING THEREFROM - Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods are also disclosed. | 11-06-2008 |
20080291027 | Thin Profile Battery Bonding Method, Method Of Conductively Interconnecting Electronic Components, Battery Powerable Apparatus, Radio Frequency Communication Device, And Electric Circuit - A curable adhesive composition is provided which comprises an epoxy terminated silane. A thin profile battery and a substrate to which the thin profile battery is to be conductively connected are also provided. The curable adhesive composition is interposed between the thin profile battery and the substrate. It is cured into an electrically conductive bond electrically interconnecting the battery and the substrate. In another aspect, the invention includes a method of conductively interconnecting electronic components using a curable adhesive composition which comprises an epoxy terminated silane. The invention in another aspect includes interposing a curable epoxy composition between first and second electrically conductive components to be electrically interconnected. At least one of the components comprises a metal surface with which the curable epoxy is to electrically connect. The epoxy is cured into an electrically conductive bond electrically interconnecting the first and second components. The epoxy has an effective metal surface wetting concentration of silane to form a cured electrical interconnection having a resistance through said metal surface of less than or equal to about 0.3 ohm-cm | 11-27-2008 |
20120175341 | METHODS FOR FORMING CONDUCTIVE ELEMENTS AND VIAS ON SUBSTRATES - Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed. | 07-12-2012 |