Patent application number | Description | Published |
20110085398 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 04-14-2011 |
20110188335 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 08-04-2011 |
20110191548 | High Utilization Multi-Partitioned Serial Memory - A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency. | 08-04-2011 |
20110191564 | Hierarchical Organization Of Large Memory Blocks - A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency. | 08-04-2011 |
20120140581 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 06-07-2012 |
20120250441 | Separate Pass Gate Controlled Sense Amplifier - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 10-04-2012 |
20120250442 | Methods For Accessing DRAM Cells Using Separate Bit Line Control - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 10-04-2012 |
20120267769 | INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS - A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively. | 10-25-2012 |
20130313723 | SEMICONDUCTOR CHIP LAYOUT WITH STAGGERED TX AND TX DATA LINESS - A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays. | 11-28-2013 |
20130336074 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 12-19-2013 |
20140119099 | DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS - A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. | 05-01-2014 |