Patent application number | Description | Published |
20100005269 | Translation of virtual to physical addresses - Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries. | 01-07-2010 |
20120089817 | Conditional selection of data elements - A data processing apparatus, method and computer program that perform an operation on one data element such as a register and then conditionally select either that register or a further register on which no operation has been performed. The apparatus comprises an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register; a data processor configured to perform data processing operations controlled by the instruction decoder wherein: the data processor is responsive to the decoded at least one conditional select instruction and the condition having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register; and the data processor is responsive to the decoded at least one conditional select instruction and the condition not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register. | 04-12-2012 |
20120239913 | DIAGNOSING CODE USING SINGLE STEP EXECUTION - A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception. | 09-20-2012 |
20130132737 | CRYPTOGRAPHIC SUPPORT INSTRUCTIONS - A data processing system | 05-23-2013 |
20140052921 | STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION - A data processing system includes a plurality of transaction masters ( | 02-20-2014 |
20140122760 | COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS - A global interrupt number space | 05-01-2014 |
20140122849 | APPARATUS AND METHOD FOR HANDLING EXCEPTION EVENTS - Processing circuitry | 05-01-2014 |
20140337585 | PAGE TABLE MANAGEMENT - Page table data for each page within a memory address space includes a write permission flag and a dirty-bit-modifier flag. The write permission flag is initialised to a value indicating that write access is not permitted. When a write access occurs, then the dirty-bit-modifier flag indicates whether or not the action of the write permission flag may be overridden. If the action of the write permission flag may be overridden, then the write access is permitted and the write permission flag is changed to indicate that write access is thereafter permitted. A page for which the write permission flag indicates that writes are permitted is a dirty page. | 11-13-2014 |
20140344621 | DIAGNOSING CODE USING SINGLE STEP EXECUTION - A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception. | 11-20-2014 |
20140351472 | METHOD AND APPARATUS FOR INTERRUPT HANDLING - A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level. | 11-27-2014 |