Patent application number | Description | Published |
20080244359 | Techniques For Correcting Errors Using Iterative Decoding - Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information. | 10-02-2008 |
20080304173 | MAGNETIC RECORDING DISK DRIVE WITH PATTERNED MEDIA AND SYSTEM FOR CLOCKING WRITE DATA - A system and method accurately clocks write data to the discrete data blocks in a patterned media disk drive. The precise time intervals between successive timing marks in the data tracks are measured by a timing mark detector that counts the integer number of write clock cycles between successive timing marks and the fractional part of a write clock cycle by detecting the phase difference between a timing mark and a reference signal. The resulting timing error is output to a write clock compensator. The write clock is capable of generating equally spaced primary phases and phases intermediate the primary phases. The compensator includes a phase rotator that controls which write clock phase is selected for output. The value in a phase register of the compensator is used to control the phase rotator to advance or retard the write clock phase, and thus to adjust its frequency and phase so as to be synchronized for writing to the data blocks. | 12-11-2008 |
20090006930 | Techniques For Generating Bit Reliability Information In The Post Processor - A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values. | 01-01-2009 |
20090006931 | Techniques For Generating Bit Reliability Information In A Post-Processor Using An Error Correction Constraint - Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values. | 01-01-2009 |
20090213484 | Techniques For Providing DC-free Detection of DC Equalization Target - A data storage device includes a first filter that generates a short DC equalization target in response to a read back signal generated from magnetic patterns that are recorded on a storage medium using perpendicular recording. The data storage device also includes a first detector that generates an output sequence in response to the short DC equalization target. The data storage device also includes a high pass filter that attenuates DC components of the short DC equalization target and that passes low frequency components of the short DC equalization target above a cutoff frequency to generate a filtered signal. The data storage device also includes a second detector that processes the output sequence in response to the filtered signal. | 08-27-2009 |
20090254796 | Techniques for correcting errors and erasures using a single-shot generalized minimum distance key equation solver - A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively processes the ordered list of candidate erasure locations and at least two syndromes of the codeword using a single-shot key equation solver to generate an error locator polynomial and an error evaluator polynomial. The generalized minimum distance decoder processes the least reliable candidate erasure locations first within the ordered list of candidate erasure locations. | 10-08-2009 |
20090274028 | Multi-bit phase alignment for synchronization mark pattern matching - Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved. | 11-05-2009 |
20090274247 | Detection of synchronization mark from output of matched filter upstream of viterbi detector - Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. According to one embodiment, synchronization marks are detected from the output of a matched filter, upstream of the Viterbi detector. This approach avoids the delay associated with the latency of the Viterbi output, thereby allowing time to align parity framing and to properly start the time-varying trellis. Certain embodiments disclose 34- and 20-bit primary synchronization marks located at the beginning of a data region. Other embodiments disclose 16-, 20-, and 24-bit embedded synchronization marks located within a data region. | 11-05-2009 |
20100235718 | Decoding Techniques for Correcting Errors Using Soft Information - Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected. | 09-16-2010 |
20120163073 | Early detection of degradation in NOR flash memory - The embodiments of the invention in this disclosure describe techniques for early warning of degradation in NOR Flash memories by estimating the dispersion of the threshold voltages (V | 06-28-2012 |
20120163074 | Early degradation detection in flash memory using test cells - A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write V | 06-28-2012 |
20120163084 | Early detection of degradation in NAND flash memory - Techniques for early detection of degradation in NAND Flash memories by measuring the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations are described. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values. In one embodiment the delta between the maximum and minimum TTC values is used as the dispersion measurement. If the measured TTC dispersion differs by more than a selected amount from a reference dispersion value, a warning signal is provided to indicate that the page of memory has degraded. The warning signal can be used to take appropriate action such as moving the data to a new page. | 06-28-2012 |
20120166707 | Data management in flash memory using probability of charge disturbances - A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population. | 06-28-2012 |
20120166897 | Data management in flash memory using probability of charge disturbances - A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population. | 06-28-2012 |
20130100550 | IMPLEMENTING MAGNETIC DEFECT CLASSIFICATION USING PHASE MODULATION - A method, apparatus, and system are provided for implementing magnetic defect classification using phase modulation for hard disk drives. A magnetic media readback signal of a hard disk drive is processed to identify predefined phase modulation (PM) characteristics to implement magnetic defect classification of magnetic media bump and pit defects. | 04-25-2013 |
20130148223 | IMPLEMENTING SPIN-TORQUE OSCILLATOR SENSING WITH ENHANCED DEMODULATOR FOR HARD DISK DRIVES - A method, apparatus, and system are provided for implementing spin-torque oscillator (STO) sensing with a demodulator for hard disk drives. The demodulator measures an instantaneous phase of the readback signal from a STO sensor and converts the readback signal into a signal that is proportional to the magnetic field affecting the STO frequency during a bit time. The converted signal is used for processing by conventional data detection electronics. | 06-13-2013 |
20130148224 | IMPLEMENTING SPIN-TORQUE OSCILLATOR SENSING WITH ENHANCED INTEGRATED DEMODULATOR FOR HARD DISK DRIVES - A method, apparatus, and system are provided for implementing spin-torque oscillator sensing with an enhanced integrated demodulator for hard disk drives. The demodulator receives an input signal from a STO read sensor having an oscillation frequency ω related to the strength of the detected magnetic signal field. The demodulator includes a pair of mixers coupled to a quadrature reference oscillator with respective quadrature components cos(ω | 06-13-2013 |
20130148229 | IMPLEMENTING SPIN-TORQUE OSCILLATOR SENSING WITH ENHANCED DELAY CONTROL FEEDBACK CIRCUIT FOR HARD DISK DRIVES - A method, apparatus, and system for implementing spin-torque oscillator (STO) sensing with an enhanced delay control feedback circuit for hard disk drives. A detector receives an input signal from a STO read sensor having an oscillation frequency related to the strength of the detected magnetic signal field. The received input signal is mixed with a time delayed input signal for providing a detector output signal. A low frequency component signal of the detector output signal is monitored and a delay control feedback is applied to an adjustable time delay to bias the DC signal of the detector output signal. | 06-13-2013 |
20130335841 | IMPLEMENTING COMBINED PHASE AND AMPLITUDE MAGNETIC DEFECT DETECTION ON-THE-FLY - A method, apparatus, and system are provided for implementing magnetic defect location detection on-the-fly for hard disk drives. A magnetic media readback signal of a hard disk drive is demodulated to generate phase modulation (PM) and amplitude modulation (AM) signals. A new coordinate plane defined by a combined phase modulation (PM) and amplitude modulation (AM) phasor-defect detector calculation function used to locate magnetic defects on-the-fly. | 12-19-2013 |
20140036381 | IMPLEMENTING TRACK FOLLOWING USING DATA CHARACTERISTICS FOR POSITIONAL INFORMATION - A method, apparatus and a data storage device are provided for implementing track following and data recovery with readback of shingled data written in overlapping shingled data tracks on a recordable surface of a storage device. Positional information is identified with data readback of shingled data written in overlapping shingled data tracks. The identified positional information is used to selectively modify at least one predefined channel parameter, for example, to provide enhanced track following and enhanced data recovery. | 02-06-2014 |
20140201590 | Disk Drive with Distributed Codeword Blocks - Disk drives are described in which blocks of data spanning multiple sectors are encoded into a plurality of codewords which are then divided into segments that are physically separated (distributed) on the disk surface over multiple sectors in a distributed codeword block so that the codewords have an improved worst case SNR in comparison to individual sectors. This results in more even SNR performance for each codeword, which improves the performance for portions of a track which have lower than the average SNR. Embodiments are described in which the distributed codeword blocks span across tracks. | 07-17-2014 |
20150077875 | DISK DRIVE WITH DIFFERENT SYNCHRONIZATION FIELDS AND SYNCHRONIZATION MARKS IN THE DATA SECTOR PREAMBLES IN ADJACENT DATA TRACKS - A hard disk drive has disks with data sector preambles that allow for inter-track interference. The same data sector preamble is used for all data sectors in a track but the preamble in each track is different from the preamble in radially adjacent tracks. In a first embodiment each preamble includes a synchronization field (SF) and synchronization mark (SM) that are the same in each track but different from the SF and SM in radially adjacent tracks. Only two unique SFs and two unique SMs are required, with the two SFs and two SMs alternating in radially adjacent tracks. In a second embodiment the preambles are “integrated”, meaning that the preamble is a sequence of bits that does not include separate dedicated fields, like SF and SM. The preamble bit sequences are decoded using matched filters to provide bit synchronization and start-of-data information. | 03-19-2015 |
20150077876 | DISK DRIVE WITH DIFFERENT DATA SECTOR INTEGRATED PREAMBLES IN ADJACENT DATA TRACKS - A hard disk drive has disks with data sector preambles that allow for inter-track interference. The same data sector preamble is used for all data sectors in a track but the preamble in each track is different from the preamble in radially adjacent tracks. In a first embodiment each preamble includes a synchronization field (SF) and synchronization mark (SM) that are the same in each track but different from the SF and SM in radially adjacent tracks. Only two unique SFs and two unique SMs are required, with the two SFs and two SMs alternating in radially adjacent tracks. In a second embodiment the preambles are “integrated”, meaning that the preamble is a sequence of bits that does not include separate dedicated fields, like SF and SM. The preamble bit sequences are decoded using matched filters to provide bit synchronization and start-of-data information. | 03-19-2015 |