Patent application number | Description | Published |
20080201541 | ON-CHIP SECURITY METHOD AND APPARATUS - A boot method an apparatus are described which reduce the likelihood of a security breach in a mobile device, preferably in a situation where a reset has been initiated. A predetermined security value, or password, is stored, for example in BootROM. A value of a security location within FLASH memory is read and the two values are compared. Polling of the serial port is selectively performed, depending on the result of such comparison. In a presently preferred embodiment, if the value in the security location matches the predetermined security value, then polling of the serial port is not performed. This reduces potential security breaches caused in conventional arrangements where code may be downloaded from the serial port and executed, which allows anyone to access and upload programs and data in the FLASH memory, including confidential and proprietary information. | 08-21-2008 |
20090132827 | DEBUGGING PORT SECURITY INTERFACE - The present invention provides a secure JTAG interface to an application-specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted. | 05-21-2009 |
20090213512 | OVER-VOLTAGE PROTECTION CIRCUIT - An over-voltage protection circuit is disclosed herein for protection against over-voltage of an energy storage device while charging. The circuit operates within the operational limits of a battery-operated device, such as a mobile or handheld device. The over-voltage protection circuit comprises an over-voltage protection device, and an over-voltage protection controller. The controller allows current to flow to the over-voltage protection device only when an energy storage device is experiencing over-voltage. In allowing current to flow to the over-voltage protection device only when the voltage across the energy storage device is above a predetermined voltage, power conservation is achieved | 08-27-2009 |
20100005232 | MEMORY CONTROLLER INTERFACE - A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. | 01-07-2010 |
20110148362 | OVER-VOLTAGE PROTECTION CIRCUIT - An over-voltage protection circuit is disclosed herein for protection against over-voltage of an energy storage device while charging. The circuit operates within the operational limits of a battery-operated device, such as a mobile or handheld device. The over-voltage protection circuit comprises an over-voltage protection device, and an over-voltage protection controller. The controller allows current to flow to the over-voltage protection device only when an energy storage device is experiencing over-voltage. In allowing current to flow to the over-voltage protection device only when the voltage across the energy storage device is above a predetermined voltage, power conservation is achieved. | 06-23-2011 |
20110302402 | ON-CHIP SECURITY METHOD AND APPARATUS - A boot method an apparatus are described which reduce the likelihood of a security breach in a mobile device, preferably in a situation where a reset has been initiated. A predetermined security value, or password, is stored, for example in BootROM. A value of a security location within FLASH memory is read and the two values are compared. Polling of the serial port is selectively performed, depending on the result of such comparison. In a presently preferred embodiment, if the value in the security location matches the predetermined security value, then polling of the serial port is not performed. This reduces potential security breaches caused in conventional arrangements where code may be downloaded from the serial port and executed, which allows anyone to access and upload programs and data in the FLASH memory, including confidential and proprietary information. | 12-08-2011 |
20120039008 | OVER-VOLTAGE PROTECTION CIRCUIT - An over-voltage protection circuit is disclosed herein for protection against over-voltage of an energy storage device while charging. The circuit operates within the operational limits of a battery-operated device, such as a mobile or handheld device. The over-voltage protection circuit comprises an over-voltage protection device, and an over-voltage protection controller. The controller allows current to flow to the over-voltage protection device only when an energy storage device is experiencing over-voltage. In allowing current to flow to the over-voltage protection device only when the voltage across the energy storage device is above a predetermined voltage, power conservation is achieved. | 02-16-2012 |
20120072651 | MEMORY CONTROLLER INTERFACE - A memory controller interface, mobile device and method are provided. The memory controller interface can allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous dynamic random access memory SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. Boot code is stored in memory accessible to the processor and is read out of the memory for execution. The boot code is scanned for a predetermined signature, and if the predetermined signature is found, a portion of the memory is write-protected. | 03-22-2012 |
20120278630 | DEBUGGING PORT SECURITY INTERFACE - The present invention provides a secure JTAG interface to an application-specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted. | 11-01-2012 |
20140013124 | ON-CHIP STORAGE, CREATION, AND MANIPULATION OF AN ENCRYPTION KEY - A system and method for encrypting data provides for retrievial of an encryption key; identification of the address in memory of a first portion of the data to be encrypted; derivation of a first unique key from the encryption key and the address of the first portion of data; encryption of the first portion of data using the first unique key; identification of the address in memory of a second portion of data to be encrypted; derivation of a second unique key from the encryption key and the address of the second portion of data; and encryption of the second portion of data using the second unique key. | 01-09-2014 |