Patent application number | Description | Published |
20100169746 | LOW-COMPLEXITY SOFT-DECISION DECODING OF ERROR-CORRECTION CODES - A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors. | 07-01-2010 |
20100174954 | NON-POLYNOMIAL PROCESSING UNIT FOR SOFT-DECISION ERROR CORRECTION CODING - A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method. | 07-08-2010 |
20100174969 | ERROR-LOCATOR-POLYNOMIAL GENERATION WITH ERASURE SUPPORT - A system and method for correcting errors in an ECC block using erasure-identification data when generating an error-locator polynomial. In an embodiment, a ECC decoding method, uses “erasure” data indicative of bits of data that are unable to be deciphered by a decoder. Such a method may use an Berlekamp-Massey algorithm that receives two polynomials as inputs; a first polynomial indicative of erasure location in the stream of bits and a syndrome polynomial indicative of all bits as initially determined. The Berlekamp-Massey algorithm may use the erasure identification information to more easily decipher the overall codeword when faced with a error-filled codeword. | 07-08-2010 |
20110075289 | HIGH-RATE TRANSITION CONTROL CODE FOR MAGNETIC RECORDING CHANNELS - A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol. | 03-31-2011 |
20110078540 | INTERLACED ITERATIVE SYSTEM DESIGN FOR 1K-BYTE BLOCK WITH 512-BYTE LDPC CODEWORDS - To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing. | 03-31-2011 |
20110083058 | TRAPPING SET BASED LDPC CODE DESIGN AND RELATED CIRCUITS, SYSTEMS, AND METHODS - A method of generating a Tanner graph includes generating a pseudo-random parameter and selecting a subgraph within the Tanner graph to be designed, and assigning new edges to the subgraph as a function of the value of the pseudo-random parameter and as a function of prior edges, if any, that have been assigned to the subgraph. The method detects whether the subgraph contains a common feature indicative of a trapping set or sets to be avoided during generation of the Tanner graph until either the common feature is not detected or all possible combination of edges have been assigned to the subgraph. The subgraph containing no occurrences of the common feature is included as part of the Tanner graph or one of combinations is selected as the subgraph and is included as part of the Tanner graph. These operations are repeated until the entire Tanner graph is generated. | 04-07-2011 |
20120075739 | HIGH-RATE TRANSITION CONTROL CODE FOR MAGNETIC RECORDING CHANNELS - A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol. | 03-29-2012 |
20140104714 | HIGH-RATE REVESE-ORDER RUN-LENGTH-LIMITED CODE - A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control. | 04-17-2014 |