Patent application number | Description | Published |
20090102019 | CONTROLLED DOPING OF SEMICONDUCTOR NANOWIRES - A catalyst particle on a substrate is exposed to reactants containing a semiconductor material in a reactor. An intrinsic semiconductor nanowire having constant lateral dimensions is grown at a low enough temperature so that pyrolysis of the reactant is suppressed on the sidewalls of the intrinsic semiconductor nanowire. Once the intrinsic semiconductor nanowire grows to a desired length, the temperature of the reactor is raised to enable pyrolysis on the sidewalls of the semiconductor nanowire, and thereafter dopants are supplied into the reactor with the reactant. A composite semiconductor nanowire having an intrinsic inner semiconductor nanowire and a doped semiconductor shell is formed. The catalyst particle is removed, followed by an anneal that distributes the dopants uniformly within the volume of the composite semiconductor nanowire, forming a semiconductor nanowire having constant lateral dimensions and a substantially uniform doping. | 04-23-2009 |
20090107964 | DEBRIS MINIMIZATION AND IMPROVED SPATIAL RESOLUTION IN PULSED LASER ABLATION OF MATERIALS - A method of minimizing the deposition of debris onto a sample being ablated. The method comprises: 1) reducing a laser pulse energy to approximately a threshold level for ablation; 2) focusing the energy using an immersion object lens having a final element and 3) ablating a region of the sample using a multitude of laser pulses, each pulse being sufficiently separated in time to reduce a concentration of ablation products in a gas phase. | 04-30-2009 |
20110309449 | INTERFACE-FREE METAL GATE STACK - A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 12-22-2011 |
20120057273 | NANOSTRUCTURE ELECTRODE FOR PSEUDOCAPACITIVE ENERGY STORAGE - A nanoporous templating substrate, which is an anodically oxidized alumina (AAO) substrate, is employed to form a pseudocapacitor having high stored energy density. A pseudocapacitive material is deposited conformally along the sidewalls of the AAO substrate by atomic layer deposition, chemical vapor deposition), and/or electrochemical deposition employing a nucleation layer. The thickness of the pseudocapacitive material on the walls can be precisely controlled in the deposition process. The AAO is etched to form an array of nanotubes of the PC material that are cylindrical and structurally robust with cavities therein. Because the AAO substrate that acts as scaffolding is removed, only the active PC material is left behind, thereby maximizing the energy per mass. In addition, nanotubes may be de-anchored from a substrate so that free-standing nanotubes having randomized orientations may be deposited on a conductive substrate to form an electrode of a pseudocapacitor. | 03-08-2012 |
20120266935 | HOMOGENIZING LIGHT-PIPE FOR SOLAR CONCENTRATORS - A light pipe that can be employed for a Concentrator Photo-Voltaic (CPV) system is provided. The light pipe homogenizes light by diffusion and/or refraction, and can be embodied in a structure that has a low aspect ratio. The diffusion and/or refraction can be effected by concave or convex surfaces of a transparent medium that forms a body of the light pipe, by light diffracting particles, and/or by a diffracting surface. Optionally, multiple transparent media can be employed with a refracting and/or diffracting interface therebetween. The reduced aspect ratio of the light pipe can improve reliability of mechanical alignment in the CPV system as well as reducing the cost of manufacturing and/or aligning the light pipe within the CPV system. | 10-25-2012 |
20120270385 | SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE - A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate. | 10-25-2012 |
20130277751 | INTERFACE-FREE METAL GATE STACK - A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 10-24-2013 |
20130280901 | INTERFACE-FREE METAL GATE STACK - A non-transitory computer readable medium encoded with a program for fabricating a gate stack for a transistor is disclosed. The program includes instructions configured to perform a method. The method includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 10-24-2013 |