Patent application number | Description | Published |
20130037928 | SEMICONDUCTOR PACKAGE AND SYSTEM - A semiconductor package includes a package board, a pellet provided over the package board, and a protection member covering the package board and the pellet and including a hole penetrating the protection member. | 02-14-2013 |
20130037947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 02-14-2013 |
20130043576 | SEMICONDUCTOR DEVICE - To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP | 02-21-2013 |
20130043948 | SEMICONDUCTOR DEVICE FOR SIGNAL AMPLIFICATION - A semiconductor device for transmitting-signal amplification which has a fine resolution, a high dynamic range, a small occupied area, and low power consumption, is realized. An input signal amplitude is reduced every one half by a ladder network, and a transconductance amplifier stage is arranged corresponding to each node of the ladder network. An output of the transconductance amplifier stage is coupled to an output signal line in common. According to a control word WC<21:0>, the transconductance amplifier stage is enabled selectively, and the output current which appears in the output signal line is added. | 02-21-2013 |
20130044530 | LAYOUT OF MEMORY CELLS AND INPUT/OUTPUT CIRCUITRY IN A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit. | 02-21-2013 |
20130054956 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface tote used in big endian or little endian mode. The first register holds control, data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status. | 02-28-2013 |
20130056849 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor and a second spiral inductor formed in the multilayer interconnect, and an interconnect substrate formed over the semiconductor chip and having a third spiral inductor and a fourth spiral inductor. The third spiral inductor overlaps the first spiral inductor in a plan view. The fourth spiral inductor overlaps the second spiral inductor in the plan view. The third spiral inductor and the fourth spiral inductor collectively include a line, the line being spirally wound in a same direction in the third spiral inductor and the fourth spiral inductor. | 03-07-2013 |
20130058167 | SEMICONDUCTOR DEVICE USING CHARGE PUMP CIRCUIT - A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element. The capacitance disconnecting circuit includes a non-volatile memory cell with a threshold voltage changed based on a change of a leakage current which flows from the capacitance element, and blocks off the leakage current based on a rise of the threshold voltage of the non-volatile memory cell when the leakage current exceeds a predetermined value. | 03-07-2013 |
20130059417 | METHOD FOR MANUFACTURING A PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR DEVICE - Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step. | 03-07-2013 |
20130059420 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained. | 03-07-2013 |
20130062689 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions. | 03-14-2013 |
20130064012 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall. The first transistor includes a portion of a logic circuit. The second transistor includes a transistor included in a memory cell of a DRAM, or includes a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM. The first gate insulating film has a same thickness as that of the second gate insulating film. The first gate electrode has the same thickness as that of the second gate electrode. A layer structure of the first sidewall is a same as a layer structure of the second sidewall. | 03-14-2013 |
20130064330 | SEMICONDUCTOR DEVICE AND COMMUNICATION DEVICE - There is a need for reducing the scale of a circuit that determines and decodes code types for reception signals coded with different codes. A reception logic circuit determines and decodes code types for reception signals coded with different codes. The reception logic circuit determines one of code types for a demodulation signal corresponding to the reception signal based on a difference between codes detected during a modulation period or a non-modulation period occurring in the demodulation signal. The reception logic circuit decodes the code type in accordance with the determined code type based on the modulation period or the non-modulation period that alternately occurs in the demodulation signal. In this manner, the received data is reproduced. There is no need for a decoder specific to each code. | 03-14-2013 |
20130065368 | NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING EMBEDDED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SIDEWALL GATE - A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation. | 03-14-2013 |
20130069249 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 03-21-2013 |
20130069723 | POWER AMPLIFICATION CIRCUIT HAVING TRANSFORMER - In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted. | 03-21-2013 |
20130071971 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided. | 03-21-2013 |
20130073765 | SEMICONDUCTOR DEVICE AND DATA PROCESSOR - In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal. | 03-21-2013 |
20130075825 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. | 03-28-2013 |
20130075858 | SEMICONDUCTOR DEVICE - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof. | 03-28-2013 |
20130075897 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit device for driving an LCD, COG chip packaging is performed. To achieve this, an elongate and relatively thick gold bump electrode is formed over an aluminum-based pad having a relatively small area. In a wafer probe test performed after formation of the gold bump electrode, a cantilever type probe needle having gold as a main component and having an almost perpendicularly bent tip portion is used. The diameter of this probe needle in the vicinity of its tip is usually almost the same as the width of the gold bump electrode. This makes it difficult to perform the wafer probe test stably. To counteract this, a plurality of bump electrode rows for outputting a display device drive signal are formed such that the width of inner bump electrodes is made greater than the width of outer bump electrodes. | 03-28-2013 |
20130075901 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad | 03-28-2013 |
20130075911 | Semiconductor Device Having Electrode/Film Opening Edge Spacing Smaller Than Bonding Pad/Electrode Edge Spacing - A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad. | 03-28-2013 |
20130076400 | COMPARATOR CIRCUIT - A comparator includes a first power source terminal, a second power source terminal, a first transistor of a first conductivity type coupled between the first power source terminal and a first node, and including a control terminal coupled to a first terminal, a second transistor of the first conductivity type coupled between the first power source terminal and a second node, and including a control terminal coupled to a second terminal, a third transistor of a second conductivity type coupled between the first node and a third terminal, and including a control terminal coupled to the first node, a fourth transistor of the second conductivity type coupled between the second node and the second power source terminal, and including a control terminal coupled to the first node, and a fourth terminal coupled to the second node. | 03-28-2013 |
20130076414 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN ON-CHIP PLL AND OPERATING METHOD THEREOF - An on-chip phase-locked loop circuit has reduced power consumption in a semiconductor integrated circuit. The phase locked loop circuit is equipped with a phase frequency comparator, a loop attenuator, a charge pump, a loop filter, a voltage controlled oscillator and a divider. The attenuator includes a sampling circuit and a counter. A sampling pulse and first and second output signals both outputted from the phase frequency comparator are supplied to the sampling circuit. The sampling circuit outputs a sampling output signal. When the counter completes a countup of a predetermined number of sampling pulses outputted from the sampling circuit, the counter outputs a countup completion output signal. The charge pump outputs a charging current or a discharging current to the loop filter in response to the countup completion output signal. | 03-28-2013 |
20130076430 | Semiconductor Integrated Circuit and Data Processing System - An arrangement for detecting local light irradiation in an illegal attack attempt to intentionally induce a malfunction or faulty condition is formed on a small chip occupancy area so as to provide high detection sensitivity. In a region containing a logic circuit, a plurality of series-coupled detection inverters are distributively disposed as photodetector elements having a constant logical value of primary-stage input. When at least one of the series-coupled detection inverters is irradiated with light, an output thereof is inverted, thereby producing a final output through the series-coupled detection inverters. Based on the final output thus produced, local light irradiation can be detected. | 03-28-2013 |
20130082783 | Semiconductor Device - Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits. | 04-04-2013 |
20130092993 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact. | 04-18-2013 |
20130093377 | PWM OUTPUT APPARATUS AND MOTOR DRIVING APPARATUS - A PWM output apparatus includes a calculating circuit configured to calculate an output width of a PWM output signal of a first signal and a second signal, which have phases different from each other, based on a command value of a PWM output. A comparing circuit compares the output width and a reference period which is set longer than a predetermined dead time period. A PWM output signal generating circuit outputs the PWM output signal to a dead time inserting block as a corrected PWM output signal, when a set/clear signal generating circuit outputs the set signal, and carries out a correction of setting the first signal of the PWM output signal to be inactive to output to the dead time inserting block as the corrected PWM output signal, when the set/clear circuit outputs the clear signal. The dead time inserting block corrects the corrected PWM output signal. | 04-18-2013 |
20130095779 | FILTER CIRCUIT AND RECEIVING DEVICE - To implement a filter circuit with low noise and a low cutoff frequency in a smaller area, a filter circuit has a first circuit which receives an input signal supplied to an input terminal, amplifies the signal, and outputs the amplified signal to an output terminal, a first differential amplification circuit for receiving the output signal of the first circuit through a first capacitance element, a first resistance element for forming a negative feedback path between the input and output of the first differential amplification circuit, and a second resistance element for forming a negative feedback path between the output of the first differential amplification circuit and the input of the first circuit. | 04-18-2013 |
20130099340 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, SIGNAL TRANSMISSION/RECEPTION METHOD USING SUCH SEMICONDUCTOR DEVICE, AND TESTER APPARATUS - A semiconductor device includes a substrate, a bonding pad provided above the substrate, a first signal transmitting/receiving portion provided above the substrate and below the bonding pad, and a transistor provided over the substrate. The transistor is connected to the first signal transmitting/receiving portion. | 04-25-2013 |
20130099381 | SEMICONDUCTOR DEVICE AND CONNECTION CHECKING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface. | 04-25-2013 |
20130100111 | DISPLAY PANEL DRIVE TECHNIQUE FOR REDUCING POWER CONSUMPTION - A method of operating a display apparatus in which one source output of a source driver is connected with first to N-th data lines through first to N-th time division switches, the method includes precharging the first to N-th data lines by outputting a predetermined precharge voltage from the source output with the first to N-th time division switches turned on, and driving a specific pixel connected with one of the first to N-th data lines, by feeding a first drive voltage to the one of the first to N-th data lines from the one source output with associated one of the first to N-th time division switches turned on. The associated one of the first to N-th time division switches is kept turned on during a period between a first timing when the precharging is started and a second timing when the driving the specific pixel is completed. | 04-25-2013 |
20130100739 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data. | 04-25-2013 |
20130102264 | SEMICONDUCTOR DEVICE AND ADJUSTMENT METHOD THEREFOR - Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing. | 04-25-2013 |
20130103328 | SCREENING DEVICE FOR SEMICONDUCTOR DEVICES, SCREENING METHOD FOR SEMICONDUCTOR DEVICES AND PROGRAM THEREOF - A screening device for semiconductor devices includes a data divider to generate measurement value subsets by sub-grouping a measurement value set including measurement results relating to characteristics of the semiconductor device based on a specific standard; a first evaluation value calculator to calculate a first evaluation value that is an evaluation standard for measurement results included in the plural respective measurement value subsets; a data converter to convert measurement results contained in the plural respective measurement value subsets based on the first evaluation value; a second evaluation value calculator to calculate a second evaluation value that is an evaluation standard for measurement results after conversion by the data converter; and a decision unit to decide if the semiconductor device under measurement is a pass or fail based on the second evaluation value. | 04-25-2013 |
20130103869 | BUS CONNECTION CIRCUIT, SEMICONDUCTOR DEVICE AND OPERATION METHOD OF BUS CONNECTION CIRCUIT - A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a mirror area access detecting circuit and a processing circuit. The mirror area access detecting circuit detects that the bus master accesses a mirror area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result. | 04-25-2013 |
20130103988 | SEMICONDUCTOR DEVICE - The disclosed invention provides a semiconductor device that enables early discovery of a sign of aged deterioration that occurs locally. An LSI has a plurality of modules and a delay monitor cluster including a plurality of delay monitors. Each delay monitor includes a ring oscillator having a plurality of gate elements. Each delay monitor measures a delay time of the gate elements. A CPU # | 04-25-2013 |
20130112852 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device includes a column ADC realizing higher precision and higher-speed conversion. Converters converts a signal of each pixels output via a corresponding vertical read line to a digital value by sequentially executing first to N-th (N: integer of three or larger) conversion stages. In the first to (N−1)th conversion stages, each converter determines a value of upper bits including the most significant bit of a digital value by comparing the voltage at a retention stage with a reference voltage while changing the voltage at a retention node. In the N-th conversion stage, each converter determines a value of remaining bits to the least significant bit by comparing the voltage at the retention node with the reference voltage while continuously changing the voltage at the retention node in a range of the voltage step in the (N−1)th conversion stage or a range exceeding the range. | 05-09-2013 |
20130113030 | SEMICONDUCTOR DEVICE - The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well. | 05-09-2013 |
20130113035 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. | 05-09-2013 |
20130113534 | CLOCK DATA RECOVERY CIRCUIT AND TRANSCEIVER SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING THE SAME - A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than −1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of −1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state. | 05-09-2013 |
20130115722 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The manufacturing efficiency of semiconductor devices is improved. A plurality of external terminals (leads) electrically coupled with a semiconductor chip, and contact regions of a plurality of terminals (test terminals) are brought into contact with each other, respectively. This establishes an electrical coupling between the semiconductor chip and a test circuit. Thus, an electrical test is performed. Herein, the terminals are to be repeatedly used in the electrical test of a plurality of semiconductor devices. Whereas, the contact region of the terminal includes a core material formed of a first alloy, and a metal film covering the core material. Further, the metal film is formed of a second alloy higher in hardness than the first alloy. | 05-09-2013 |
20130119454 | NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE - A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. | 05-16-2013 |
20130119469 | SEMICONDUCTOR DEVICE - Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor. | 05-16-2013 |
20130119470 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. | 05-16-2013 |
20130119537 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density, and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array. The plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density. | 05-16-2013 |
20130119967 | BANDGAP REFERENCE CIRCUIT AND POWER SUPPLY CIRCUIT - A BGR circuit includes a first bipolar transistor and a second bipolar transistor that are connected between a power supply terminal and a ground terminal, each base of the first bipolar transistor and the second bipolar transistor being connected to an output terminal. A first resistor is connected between the ground terminal and the first bipolar transistor. A second resistor and a third resistor are connected in series between the first resistor and the second bipolar transistor. A temperature correction circuit is connected between the ground terminal and a node between the second resistor and the third resistor, and includes a first transistor having a base connected to an end of the first bipolar transistor of the first resistor. The temperature correction circuit further includes a fourth resistor connected in series to the first transistor. | 05-16-2013 |
20130120178 | SEMICONDUCTOR DEVICE AND SENSOR SYSTEM - A semiconductor device includes an analog front-end unit that performs analog front-end processing of a measurement signal input from a sensor, where circuit configuration and circuit characteristics for performing the analog front-end processing are changeable, and an MCU unit that converts the measurement signal after the analog front-end processing from analog to digital and sets circuit configuration and circuit characteristics to the analog front-end unit. | 05-16-2013 |
20130120431 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND PROGRAM PRODUCT - A transformation rule of color transformation in an appropriate color space is set even without advanced knowledge and know-how. A three-dimensional lookup table unit transforms color information on an input image signal on the basis of a transformation rule. A correction range calculation unit calculates a correction range in a predetermined color space on the basis of a positional relationship between source coordinates and destination coordinates in the color space. A lattice point transfer distance calculation unit calculates the transformation destination coordinates at respective points on the basis of the positional relationship between the source coordinates and the destination coordinates, and a positional relationship between coordinates at the respective points within the correction range and the source coordinates to reflect the calculated transformation destination coordinates on the transformation rule. | 05-16-2013 |
20130120699 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE DEVICE, AND LIQUID CRYSTAL DISPLAY - In order to shield the light incident from the chip side surface or chip rear surface of a semiconductor chip that forms an LCD driver, a light-shielding film is formed over the chip side surface and chip rear surface of the semiconductor chip itself, not using a light-shielding tape that is a component separate from the semiconductor chip. Accordingly, the light-shielding tape as a separate component is not used, and hence the trouble that the light-shielding tape may protrude from the surface of a glass substrate whose thickness has been made small can be solved. As a result, the thinning of a liquid crystal display, and the subsequent thinning of the mobile phone in which the liquid crystal display is mounted can be promoted. | 05-16-2013 |
20130121095 | MEMORY CONTROLLER, SYSTEM INCLUDING THE CONTROLLER, AND MEMORY DELAY AMOUNT CONTROL METHOD - A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system LSI, the delay set value being based on the test pattern, storing the delay set value after the power source of the system LSI is turned off and outputting the stored delay set value to the system LSI, if the power source of the system LSI is turned on again. | 05-16-2013 |
20130122615 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed. | 05-16-2013 |
20130122662 | ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT - A method of manufacturing an electronic component, wherein a resin including colored particles composing dots in a dot pattern which will act as an authentication pattern is flowed in and solidified over the electronic component, thereby fixing the colored particles. | 05-16-2013 |
20130124790 | MEMORY MODULE, CACHE SYSTEM AND ADDRESS CONVERSION METHOD - A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips. | 05-16-2013 |
20130125085 | DEVELOPMENT SUPPORT APPARATUS OF SEMICONDUCTOR DEVICE, DEVELOPMENT SUPPORT METHOD, AND DEVELOPMENT SUPPORT PROGRAM PRODUCT - Disclosed is a development support apparatus of a semiconductor device that makes it possible to easily develop the semiconductor device, a development support method, and a program product. A design evaluation apparatus is a design evaluation apparatus having an analog front-end unit for inputting a measurement signal of a sensor and an MCU unit, which has a GUI processing unit for displaying a GUI corresponding to a circuit configuration of the analog front-end unit and a register setting unit that generates setting information for setting up the circuit configuration and a circuit characteristic of the analog front-end unit based on an operation of the GUI by a user, and sets the generated setting information in the analog front-end unit through the MCU unit. | 05-16-2013 |
20130126893 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region). | 05-23-2013 |
20130126960 | Semiconductor Device and Method of Manufacturing the Same - Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d | 05-23-2013 |
20130126965 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset. | 05-23-2013 |
20130127050 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip. | 05-23-2013 |
20130127428 | DC-DC CONVERTER - A DC-DC converter includes a first switching element and a second switching element; a pulse signal generating circuit which generates a pulse signal used to control on/off periods of the switching elements; a limiting circuit which generates a minimum pulse width signal; a selector configured to select one of the pulse signal and the minimum pulse width signal, and a driver circuit switches the first and second switching element and a reverse current detecting circuit detects a reverse current. The driver circuit controls the first or second switching element, when the reverse current is detected. The selector selects the pulse signal when the reverse current is not detected, and selects the minimum pulse width signal when the reverse current is detected. | 05-23-2013 |
20130127695 | Display Control Drive Device and Display System - A display control drive device sequentially reads display data from a display memory in which the display data is stored, produces three primary color image signals that are applied to pixel locations in a dot-matrix color display device, and transmits the signals through a common external output terminal in a time-sharing manner. The display control drive device produces control signals applied to selection switching elements in the display device and that selectively apply an input image signal to any of three source lines. The display control drive device includes: a unit that determines one horizontal period based on a clock received from outside synchronously with display data; and a signal production circuit that produces and transmits the control signals, applied to the selection switching elements, so that the control signals will have a pulse duration equivalent to a time calculated by trisecting one horizontal period. | 05-23-2013 |
20130128938 | RECEIVING DEVICE, SIGNAL PROCESSING DEVICE, AND SIGNAL PROCESSING METHOD - A receiving device according to the present invention includes: a receiver for receiving an OFDM symbol that is modulated by phase shift keying; an FFT processor for applying an FFT process to the received OFDM symbol to obtain a subcarrier signal; a demapping unit for demapping the subcarrier signal to generate a bit string; a norm calculator for calculating the norm of the subcarrier; a weighting factor generator for generating a weighting factor by taking the statistics of the calculated norm; and a weighting unit for obtaining a soft decision value by weighting the bit string after demapping, based on the particular weighting factor. Thus, the receiving device can obtain a soft decision value to achieve good decoding performance with a small number of known signals and processes. | 05-23-2013 |
20130130408 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape. | 05-23-2013 |
20130132451 | POWER SUPPLY CONTROL APPARATUS - A power supply control apparatus includes a first adder configured to generate a difference signal based on a target value and a feedback signal; a compensator having a first transfer function Wc(z) and configured to generate a control signal based on the difference signal; a control target having a second transfer function Wp(z) and configured to output an output signal generated in response to the control signal; a disturbance canceller having a third transfer function {1+Wc(z)·Wp(z)}/{Wc(z)·Wp(z)} and configured to generate a disturbance cancelling signal based on the output signal corresponding to a control amount y; a second adder configured to generate a differential disturbance signal based on an output of the first adder and the disturbance cancelling signal; and a filter circuit which generates the feedback signal based on the differential disturbance signal. | 05-23-2013 |
20130134418 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view. | 05-30-2013 |
20130134500 | POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. | 05-30-2013 |
20130134549 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film. | 05-30-2013 |
20130134959 | CONTROLLER - The disclosed invention provides a controller that can prevent overshoot and undershoot from occurring when a voltage is switched to another voltage without using two types of regulators. Voltage regulators supply a power supply voltage to a CPU. An SVID interface receives a command to change the number of voltage regulators to be actuated among the voltage regulators from outside. A phase clock generating circuit makes a stepwise change of the number of voltage regulators to be actuated from the current number of regulators to the commanded number of regulators after change. | 05-30-2013 |
20130135036 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate. | 05-30-2013 |
20130135076 | TRANSFORMER - A second inductor is disposed opposite to a first inductor and rotated around the center axis by 180°. The first inductor includes a plurality of lines concentrically formed in a first wiring layer, and a first intersection that is formed in a first area and connects a first line with a second line. The first intersection includes a first connection line formed in a second wiring layer, and a first interlayer line connecting the first and second lines with the first connection line. The second inductor includes a plurality of lines concentrically formed in a third wiring layer, and a second intersection that is formed in a second area and connects a third line with a fourth line. The second intersection includes a second connection line formed in a fourth wiring layer, and a second interlayer line connecting the third and fourth lines with the second connection line. | 05-30-2013 |
20130135921 | SEMICONDUCTOR MEMORY DEVICE - A first ReRAM unit having a resistance change layer is provided between a first access transistor configuring the SRAM and a first bit line, and a second ReRAM unit having a resistance change layer is provided between a second access transistor and a second bit line. When a low potential (L=0V) is held at a first storage node and a high potential (H=1.5V) is held at a second storage node at the end of a normal operation period of the SRAM, the first ReRAM unit is set to ON state (ON), and the second ReRAM unit is set to OFF state (OFF); accordingly, the retained data of the SRAM is written in to the ReRAM units. When the SRAM returns to the normal operation again, data corresponding to the storage nodes are written back and the ReRAM units are both set to ON state (reset). | 05-30-2013 |
20130137223 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 05-30-2013 |
20130137231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. | 05-30-2013 |
20130138928 | VLIW PROCESSOR, INSTRUCTION STRUCTURE, AND INSTRUCTION EXECUTION METHOD - A first operation unit | 05-30-2013 |
20130140669 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. | 06-06-2013 |
20130140717 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a layer and another one of the ground lines extending from the one of the ground lines toward another direction in the layer, a first pad on the multi-layer wiring layer, and a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first pad and the second pad, and an insulation film covering the redistribution line. | 06-06-2013 |
20130141403 | DATA DRIVER, DISPLAY PANEL DRIVING DEVICE, AND DISPLAY DEVICE - To reduce current noise by reducing the current peak value and the current rise slope, a data driver includes a delay unit and a plurality of output circuits. The delay unit sequentially delays a control signal and outputs delay control signals. The output circuits start outputting in response to the delay control signals. The delay unit generates the delay control signals to be output to the output circuits. | 06-06-2013 |
20130141449 | IMAGE PROCESSING CIRCUIT, AND DISPLAY PANEL DRIVER AND DISPLAY DEVICE MOUNTING THE CIRCUIT - A circuit includes an image decompression circuit configured to receive compressed image data which are generated by compressing image data of a set of pixels of a target block by using a selected compression method selected from a plurality of compression methods based on a correlation among said image data of said set of pixels of said target block, and to generate decompressed image data by decompressing said compressed image data by using a decompression method corresponding to said selected compression method. | 06-06-2013 |
20130141990 | MEMORY CONTROL DEVICE - A memory control device that can reduce a power consumption at the time of writing a memory. The memory control device includes a data output buffer circuit that burst-transfers data to a memory device through a data bus, and a mask signal output buffer circuit that outputs, to the memory device, a mask signal indicative of data that prohibits write into a memory cell within the memory device among the data. The data output buffer circuit puts an output node into a high impedance state when the mask signal is indicative of write prohibition. | 06-06-2013 |
20130143359 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured. | 06-06-2013 |
20130145081 | SEMICONDUCTOR DEVICE WITH NON-VOLATILE MEMORY AND RANDOM ACCESS MEMORY - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data. | 06-06-2013 |
20130146941 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film. | 06-13-2013 |
20130147039 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween. | 06-13-2013 |
20130147064 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. | 06-13-2013 |
20130149825 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps. | 06-13-2013 |
20130149837 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced. | 06-13-2013 |
20130149855 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film. | 06-13-2013 |
20130153959 | SEMICONDUCTOR DEVICE - An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in FIG. | 06-20-2013 |
20130154075 | SEMICONDUCTOR DEVICE - In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur. | 06-20-2013 |
20130154126 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which can change electrode pads of a semiconductor chip which are allocated to balls without any increase in the number of wires and without any change in a substrate. The semiconductor device includes a semiconductor chip having first and second electrode pads, and a package substrate on which the semiconductor chip is mounted. The package substrate includes a first stitch having a width larger than widths of first and second wires, a second stitch having a width larger than the widths of the first and second wires, a ball that can be coupled with an external, the first wire that couples the first stitch and the ball, and the second wire that couples the first stitch and the second stitch. A first bonding wire couples the first stitch and the first electrode pad, or the second stitch and the second electrode pad. | 06-20-2013 |
20130154697 | PLL CIRCUIT - A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator. | 06-20-2013 |
20130158371 | BIOELECTRICAL IMPEDANCE MEASURING APPARATUS, SEMICONDUCTOR DEVICE, AND CONTROL METHOD FOR BIOELECTRICAL IMPEDANCE MEASURING APPARATUS - A current supply unit supplies a current between first and second current output terminals. A voltage measurement unit measures a voltage input to first and second voltage input terminals. A control circuit causes a first switch unit to connect the first current output terminal to a first terminal of a reference resistor and to connect the second current output terminal to a second terminal of the reference resistor, causes a second switch unit to connect the first voltage input terminal to the first terminal of the reference resistor and to connect the second voltage input terminal to the second terminal of the reference resistor, and causes a voltage measurement unit to measure a voltage between the first and second voltage input terminals, thereby performing self-diagnosis of a path through which a current flows. | 06-20-2013 |
20130159577 | SEMICONDUCTOR DATA PROCESSING DEVICE, TIME-TRIGGERED COMMUNICATION SYSTEM, AND COMMUNICATION SYSTEM - The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request. | 06-20-2013 |
20130159783 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - Provided is a semiconductor device including: a first memory that stores multiple instructions; a second memory that stores multiple data items; first and second buses; a microprocessor that fetches, through the first bus, an instruction at a specified address among the multiple instructions stored in the first memory, executes the instruction, and accesses the second memory through the second bus based on a result of the execution; and a trace information output unit that acquires, when a branch instruction is generated in the microprocessor, address information of the first memory specified before branching, and outputs the information as trace information. The trace information output from the trace information output unit is written into the second memory through the second bus in a period in which the microprocessor does not access the second memory during execution of the branch instruction. | 06-20-2013 |
20130161753 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET. | 06-27-2013 |
20130162294 | LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE - In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage. | 06-27-2013 |
20130162295 | CLOCK GENERATOR INTERMITTENTLY GENERATING SYNCHRONOUS CLOCK - A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal. | 06-27-2013 |
20130162458 | AD CONVERTER AND SOLID-STATE IMAGING APPARATUS USING THE SAME - There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached. | 06-27-2013 |
20130164927 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded. | 06-27-2013 |
20130166878 | VECTOR SIMD PROCESSOR - Operation parallelism of a data processor is enhanced by floating-point inner product execution units compatible with single instruction multiple data (SIMD). An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining efficiency of floating-point length-4 vector inner product execution units is implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle. | 06-27-2013 |
20130168690 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms. | 07-04-2013 |
20130168817 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer. | 07-04-2013 |
20130170304 | MEMORY INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE - There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. | 07-04-2013 |
20130171776 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package. | 07-04-2013 |
20130175611 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate. | 07-11-2013 |
20130175636 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a transistor formed over the substrate, insulating layers formed over the substrate, a multilayer wiring formed in the insulating layers, a first inductor formed in the insulating layers, and a second inductor formed over the first inductor and overlapping the first inductor. The insulating layers contain a silicon, wherein at least the two insulating layers are formed between the first inductor and the second inductor, and the first inductor and the second inductor are a spiral wiring pattern. | 07-11-2013 |
20130176765 | ONE-TIME PROGRAMABLE CELL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DATA JUDGING METHOD THEREOF - Provided is a semiconductor integrated circuit including: an anti-fuse element that electrically connects a first node and a first power supply terminal when data is written and electrically disconnect the first node and the first power supply terminal when data is not written; a first switch circuit that is connected between the first node and a first data line applied with a predetermine first voltage, and enters an off state from an on state according to a first control signal; and a detection part that detects write data of the anti-fuse element according to whether a voltage of the first node is substantially the same as the first voltage or substantially the same as a supply voltage of the first power supply terminal when the first switch circuit enters the off state. | 07-11-2013 |
20130179606 | INFORMATION PROCESSOR SYSTEM - In an information processor system including a memory device (MEM | 07-11-2013 |
20130181111 | LIGHT MEASURING CIRCUIT AND METHOD - A light measuring circuit includes an integration circuit for integrating a current supplied form a photoelectric conversion element, an AD converter for AD converting the output voltage of the integration circuit, and a controller for obtaining a first AD conversion result from the AD converter and controlling the integration circuit and the AD converter to determine the time constant of the integration circuit in a second AD conversion following a first AD conversion. In this way, it is possible to measure the photocurrent with a wide dynamic range without making the circuit more complicated. | 07-18-2013 |
20130181765 | DECOUPLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes. | 07-18-2013 |
20130182482 | CONTENT ADDRESSABLE MEMORY DEVICE - A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance. | 07-18-2013 |
20130182497 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device having tunnel magnetoresistive elements in memory cells. | 07-18-2013 |
20130182747 | CLOCK CONTROL CIRCUIT, DEMODULATION DEVICE AND SPREAD SPECTRUM METHOD - To provide a clock control circuit, a demodulation device, and a spread spectrum method, which can reduce interference caused by a clock signal on which spread spectrum is performed when demodulating a signal. A clock controller | 07-18-2013 |
20130182804 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF - To reduce the time of reception operation switching between multiple wireless systems, a semiconductor integrated circuit includes a first reception unit including a first analog reception unit and a first digital reception unit, and a digital interface. The first analog reception unit includes a first reception mixer and a first A/D converter, and the first digital reception unit includes a first digital filter. The first reception unit, an oscillator, and a PLL enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system. In a period of an end transition operation of the first digital reception unit in the switching, the PLL starts a lock operation so as to match a frequency of an oscillation output signal generated from the oscillator to a desired frequency of the second system. | 07-18-2013 |
20130185042 | SIMULATION DEVICE AND SIMULATION PROGRAM - A simulation device and simulation program are provided that can be suitably applied to a manufacturing process including a plurality of processing steps. The simulation device is provided for simulating the manufacturing process including a first processing step using a first mask, and a second processing step using a second mask. The simulation device includes first obtaining means for obtaining a first intensity distribution generated over a substrate of interest for processing by the first mask, second obtaining means for obtaining a second intensity distribution generated over the substrate by the second mask, and revising means for revising an intensity of a region in the first intensity distribution to be processed by the second mask, to a value regarded as a region not to be processed, based on the second intensity distribution. | 07-18-2013 |
20130185462 | USB 3.0 DEVICE AND CONTROL METHOD THEREOF - A control unit of a USB 3.0 device controls the USB 3.0 device that has entered an SS.Disabled state to transition to an Rx.Detect state when a USB 2.0 connection is not established after a predetermined time, in which the USB 2.0 connection is one of an HS (High Speed) connection, an FS (Full Speed) connection, and an LS (Low Speed) connection. This enables quick return to the Rx.Detect state for the USB 3.0 device that entered the SS.Disabled state due to an error in the host. | 07-18-2013 |
20130185468 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a first module that issues a first transaction from a first interface unit to be a bus master, a second module that includes a second interface unit to be a bus slave and a third interface unit to be a bus master, and issues a second transaction in response to the first transaction, a third module that receives the second transaction by a fourth interface unit to be a bus slave, a bus master stop request control unit that asserts a bus master stop request and completes an assertion process in response to assertion of a bus master stop acknowledgement, and a code addition unit that adds to the first transaction a compulsory process request code for forcing issuance of the second transaction regardless of the bus master stop request. | 07-18-2013 |
20130187223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 07-25-2013 |
20130187230 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. | 07-25-2013 |
20130187248 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY - The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film. | 07-25-2013 |
20130189835 | METHOD FOR CLEANING A SEMICONDUCTOR DEVICE - A method of cleaning a semiconductor device that both inhibits dissolution of gate metal material and acquires favorable contact resistance. The gate of the device is multilayered, with stacked layers of metal and silicide beneath an insulation layer and atop a silicon substrate. A shared contact hole formed in the insulation layer exposes the silicide layer and multilayer gate from the insulation layer. The shared contact hole is subjected to sulfuric acid, aqueous hydrogen peroxide and APM cleaning processes, separately, to remove an altered layer that tends to form in the shared contact hole. | 07-25-2013 |
20130191587 | MEMORY CONTROL DEVICE, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A memory control device includes a first memory, a second memory, a third memory longer in a delay time since start-up until an actual data access, and a control unit. The second memory stores at least a part of data from each data string among multiple data strings with a given number of data as a unit. The third memory stores all of data within the plurality of data strings therein. If a cache miss occurs in the first memory, the control unit conducts hit determination of a cache in the second memory, and starts an access to the third memory. If the result of the hit determination is a cache hit, the control unit reads the part of data falling under the cache hit from the second memory as leading data, reads data other than the part of data, of a data string to which the part of data belongs, from the third memory, and makes a response as subsequent data to the leading data. | 07-25-2013 |
20130191657 | DEBUG SYSTEM, ELECTRONIC CONTROL UNIT, INFORMATION PROCESSING UNIT, SEMICONDUCTOR PACKAGE, AND TRANSCEIVER CIRCUIT - Disclosed is a debug system that suppresses the supply of extra electrical power for functions disused in the future while maintaining the performance of communication between an electronic control unit and an external unit for development. The debug system includes an electronic control unit that has a microcomputer for controlling the operation of a control target, a transceiver circuit that is capable of communicating data with the microcomputer, and an external unit for development that is capable of rapidly communicating data with the transceiver circuit. The electronic control unit includes a power supply unit for supplying electrical power to the microcomputer. The transceiver circuit operates on electrical power supplied from an external power supply unit, which differs from the power supply unit included in the electronic control unit. | 07-25-2013 |
20130193438 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 08-01-2013 |
20130194024 | SEMICONDUCTOR DEVICE AND COMMUNICATION INTERFACE CIRCUIT - A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors. | 08-01-2013 |
20130194882 | SEMICONDUCTOR DEVICE HAVING TIMING CONTROL FOR READ-WRITE MEMORY ACCESS OPERATIONS - A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device | 08-01-2013 |
20130198486 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a first address generation unit that includes a first register group and generates a table address by a cyclically repeating first pattern using a value stored to the first register group, a second address generation unit that includes a second register group and generates an access address by a cyclically repeating second pattern using a value stored to the second register group and parameter information determined by the table address, and a control unit that outputs setting information to be supplied to the first register group and the second register group. Further, the semiconductor device performs at least one of a read process and a write process of data from and to a data memory using the access address. | 08-01-2013 |
20130198539 | WATCHDOG CIRCUIT, POWER IC AND WATCHDOG MONITOR SYSTEM - A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation. | 08-01-2013 |
20130200935 | SEMICONDUCTOR DEVICE HAVING CMOS TRANSFER CIRCUIT AND CLAMP ELEMENT - A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal. | 08-08-2013 |
20130201044 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSING SYSTEM - The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer. | 08-08-2013 |
20130203217 | SEMICONDUCTOR DEVICE - The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other. | 08-08-2013 |
20130205058 | MULTI-THREAD PROCESSOR AND ITS INTERRUPT PROCESSING METHOD - A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated. | 08-08-2013 |