Patent application number | Description | Published |
20080290505 | MOLD DESIGN AND SEMICONDUCTOR PACKAGE - A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation. | 11-27-2008 |
20080290509 | Chip Scale Package and Method of Assembling the Same - A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip. | 11-27-2008 |
20080293186 | METHOD OF ASSEMBLING A SILICON STACK SEMICONDUCTOR PACKAGE - A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of a second die; wherein the first and second dies have a plurality of conductive protrusions on the bottom surfaces of the dies; wherein the first die has a plurality of conductive vias extending from its conductive protrusions, through the first die, to the top surface of the first die; wherein the conductive vias of said first die are in alignment with the conductive protrusions of the second die; and heating the dies and the substrate to cause the second die to become electrically interconnected to the first die and the first die to become electrically connected to the substrate. | 11-27-2008 |
20080303031 | VENTED DIE AND PACKAGE - A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly. | 12-11-2008 |
20080303163 | THROUGH SILICON VIA DIES AND PACKAGES - A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings. | 12-11-2008 |
20090004777 | Stacked die semiconductor package and method of assembly - A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly. | 01-01-2009 |
20090072391 | Structurally-enhanced integrated circuit package and method of manufacture - A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps. | 03-19-2009 |
20100013081 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 01-21-2010 |
20100109142 | INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact. | 05-06-2010 |
20100109169 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly. | 05-06-2010 |
20120018869 | MOLD DESIGN AND SEMICONDUCTOR PACKAGE - A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation. | 01-26-2012 |
20120104628 | INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact. | 05-03-2012 |
20120149150 | VENTED DIE AND PACKAGE - A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly. | 06-14-2012 |
20130119560 | PACKAGING STRUCTURAL MEMBER - A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate. | 05-16-2013 |
20140045301 | THROUGH SILICON VIA DIES AND PACKAGES - A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings. | 02-13-2014 |