Patent application number | Description | Published |
20100019351 | VARACTORS WITH ENHANCED TUNING RANGES - A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer. | 01-28-2010 |
20100079200 | PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANALOG CIRCUITS USING A SINGLE PROCESS - A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors. | 04-01-2010 |
20100090308 | METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS - Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor. | 04-15-2010 |
20100127331 | ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS - Mixed gate metal-oxide-semiconductor transistors are provided. The transistors may have an asymmetric configuration that exhibits increased output resistance. Each transistor may be formed from a gate insulating layer formed on a semiconductor. The gate insulating layer may be a high-K material. Source and drain regions in the semiconductor may define a transistor gate length. The gate length may be larger than the minimum specified by semiconductor fabrication design rules. The transistor gate may be formed from first and second gate conductors with different work functions. The relative sizes of the first and gate conductors in a given transistor control the threshold voltage for the transistor. A computer-aided design tool may be used to receive a circuit design from a user. The tool may generate fabrication masks for the given design that include mixed gate transistors with threshold voltages optimized to meet circuit design criteria. | 05-27-2010 |
20100127332 | INTEGRATED CIRCUIT TRANSISTORS - Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor. | 05-27-2010 |
20120235662 | VERY LOW VOLTAGE REFERENCE CIRCUIT - A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt. | 09-20-2012 |
Patent application number | Description | Published |
20080225601 | EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 09-18-2008 |
20080273392 | METHOD OF PROGRAMMING A SELECTED MEMORY CELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
20080273401 | METHOD OF ERASING A BLOCK OF MEMORY CELLS - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
20090014772 | EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 01-15-2009 |