| Patent application number | Description | Published |
|---|
| 20090172054 | EFFICIENT LEADING ZERO ANTICIPATOR - Embodiments of the present invention provide a system that estimates the location of the leading zero or the leading one in the result of an addition of floating-point numbers A and B. The system includes a half-adder circuit associated with each separate bit position i in A and B. The half-adder circuits compute a sum (S) for the associated bit position of A and B and a carry (K) for a next bit position of A and B. The system also includes a set of estimation circuits coupled to the set of half-adder circuits. The set of estimation circuits computes an estimate for the location of the leading zero or the leading one in the result from the K and S computed by each half-adder circuit. | 07-02-2009 |
| 20090287757 | Leading Zero Estimation Modification for Unfused Rounding Catastrophic Cancellation - Modifying a leading zero estimation during an unfused multiply add operation of (A*B)+C. A plurality of terms x and y may be received, and each may be based on truncated terms s and t (e.g., in performing the unfused multiply add operation) and the shifted C term. A first leading zero estimation may be calculated based on the terms x and y. It may be determined if near total catastrophic cancellation has occurred. A carry in from a right most number of bits of the terms s and t and the most significant truncated bits of s and t may be used to generate a second leading zero estimation based on the first leading zero estimation if the near total catastrophic cancellation has occurred. | 11-19-2009 |
| 20100036901 | MODULUS-BASED ERROR-CHECKING TECHNIQUE - During a method, a modulus circuit determines a modulus base p of a first number and a modulus base p of a second number. Also, the modulus circuit performs the operation using the modulus base p of the first number and the modulus base p of the second number, and calculates a modulus base p of the result of the operation involving the first number and the second number. Next, the modulus circuit compares the result of the operation carried out on the modulus base p of the first number and the modulus base p of the second number with the modulus base p of the operation performed on the first number and the second number to identify potential errors associated with the operation. Moreover, the modulus circuit repeats the method to identify additional potential errors associated with the operation, where the determining and calculating operations are repeated using moduli base q. | 02-11-2010 |
| 20100057824 | METHOD AND SYSTEM FOR PROCESSING THE BOOTH ENCODING 33RD TERM - A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result, a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero, and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term. The shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation. | 03-04-2010 |
| 20100329450 | INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS - Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor. | 12-30-2010 |
