Patent application number | Description | Published |
20090249036 | EFFICIENT METHOD AND APPARATUS FOR EMPLOYING A MICRO-OP CACHE IN A PROCESSOR - Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache. | 10-01-2009 |
20100115240 | Optimizing performance of instructions based on sequence detection or information associated with the instructions - In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed. | 05-06-2010 |
20100115248 | Technique for promoting efficient instruction fusion - A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction. | 05-06-2010 |
20100138608 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor - Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache. | 06-03-2010 |
20100138610 | METHOD AND APPARATUS FOR INCLUSION OF TLB ENTRIES IN A MICRO-OP CACHE OF A PROCESSOR - Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss. | 06-03-2010 |
20100138611 | METHOD AND APPARATUS FOR PIPELINE INCLUSION AND INSTRUCTION RESTARTS IN A MICRO-OP CACHE OF A PROCESSOR - Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache. | 06-03-2010 |
20130275733 | MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES - This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state. | 10-17-2013 |
20130346728 | Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions - In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed. | 12-26-2013 |
20140189330 | OPTIONAL BRANCHES - Branch instructions are provided for improved execution performance. The branch instruction includes one or more paths that are marked as a safe path for execution. If a marked path is executed based on a branch prediction, the execution continues until completion after it is determined that the other path is the correct path. | 07-03-2014 |
20140189331 | SYSTEM OF IMPROVED LOOP DETECTION AND EXECUTION - An method may include identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination of whether the last iteration of the loop is done. If the last iteration is not done, then continue replaying the loop instructions, until the last iteration is done. | 07-03-2014 |
20140245273 | PROTECTING THE INTEGRITY OF BINARY TRANSLATED CODE - The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid. | 08-28-2014 |
20140298140 | APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY - An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. | 10-02-2014 |
Patent application number | Description | Published |
20100023739 | METHOD AND APPARATUS FOR BOOTING A PROCESSING SYSTEM - Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether an encrypted version of a closed operating system is authentic may be determined. The encrypted version of the closed operating system may be decrypted with a key retrieved from a processor register to provide the closed operating system, based at least in part on a determination that the encrypted version of the closed operating system is authentic. Then, whether the closed operating system is authentic may be determined and a virtual machine may be created so that the closed operating system may be launched in the virtual machine, if the closed operating system is authentic. | 01-28-2010 |
20110016290 | Method and Apparatus for Supporting Address Translation in a Multiprocessor Virtual Machine Environment - In one embodiment, a method includes receiving control of a first processor transitioned from a virtual machine due to a privileged event pertaining to a translation-lookaside buffer, and determining which entries in a guest translation data structure were modified by the virtual machine. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor and attributes associated with entries in the shadow translation data structure. The metadata includes an active entry list identifying mappings that map pages used by a guest operating system in forming the guest translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure, and determining which entries to keep in the active entry list, based at least in part on attributes associated with corresponding entries in the shadow translation data structure identifying which of the plurality of processors owns each entry in the active entry list. | 01-20-2011 |
20140297962 | INSTRUCTIONS AND LOGIC TO PROVIDE ADVANCED PAGING CAPABILITIES FOR SECURE ENCLAVE PAGE CACHES - Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave. | 10-02-2014 |