Raorane
Deepak Raorane, Maharashtra IN
Patent application number | Description | Published |
---|---|---|
20120247933 | SWITCHGEAR ASSEMBLY - A switchgear assembly includes a tank housing encapsulating switching contacts which are viewable through a transparent viewing port after illumination of the contacts. A reflective optical device for observing the position of the switching contacts is used to view the contacts at a safe distance outside of the tank housing through the transparent viewing port. An illuminating device is used to illuminate the switching contacts by directing the light from the illuminating device on the switch contacts. | 10-04-2012 |
Deepak Rajaram Raorane, Vadodara IN
Patent application number | Description | Published |
---|---|---|
20130329325 | METHOD AND SYSTEMS FOR DISCHARGING ENERGY FROM AN ELECTRICAL FAULT - An electrical fault mitigation system includes a mitigation device including a containment chamber defining a cavity, a first electrode positioned within the cavity and coupled to a first conductor, and a second electrode positioned within the cavity and coupled to a second conductor. The mitigation device also includes a first voltage source, and a plasma gun positioned within the cavity and configured to emit ablative plasma using the first voltage source to discharge energy from an electrical fault. The system also includes a first voltage limiter device configured to limit a voltage of the first conductor from increasing above a predetermined threshold to prevent a second voltage source from generating a second electrical arc between the first electrode and the second electrode when the second voltage source applies a voltage across the first electrode and the second electrode. | 12-12-2013 |
Digvijay Raorane, Chandler, AZ US
Patent application number | Description | Published |
---|---|---|
20110201205 | METHOD OF FORMING A DEEP TRENCH IN A SUBSTRATE - Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers. | 08-18-2011 |
20110217832 | METHOD OF FILLING A DEEP TRENCH IN A SUBSTRATE - Methods of filling deep trenches in substrates are described. A method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing at least a portion, but not all, of the dielectric layer at the top of the deep trench with a relatively low bias plasma etch process. | 09-08-2011 |
Digvijay A. Raorane, Berkeley, CA US
Patent application number | Description | Published |
---|---|---|
20120108450 | Receptors Useful for Gas Phase Chemical Sensing - The invention provides for a receptor, capable of binding to a target molecule, linked to a hygroscopic polymer or hydrogel; and the use of this receptor in a device for detecting the target molecule in a gaseous and/or liquid phase. The invention also provides for a method for detecting the presence of a target molecule in the gas phase using the device. In particular, the receptor can be a peptide capable of binding a 2,4,6-trinitrotoluene (TNT) or 2,4-dinitrotoluene (DNT). | 05-03-2012 |
Digvijay A. Raorane, Chandler, AZ US
Patent application number | Description | Published |
---|---|---|
20140264830 | BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THIN DIELECTRIC LAYER - Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via. | 09-18-2014 |
20140332975 | MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED IN PACKAGE - Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed. | 11-13-2014 |