Patent application number | Description | Published |
20100129433 | Proteoliposome, Production Method Thereof, and Biochip - A proteoliposome, which is obtained by removing a surfactant from a mixed solution including lipid, membrane proteins and the surfactant, wherein the content of the surfactant in the mixed solution is equal to or more than 1.5 times of the sum of a maximum amount of the surfactant associating with the lipid and a maximum amount of the surfactant associating with the membrane protein. A biochip wherein the above-described proteoliposome is spread on a substrate. A method for producing a proteoliposome by removing a surfactant from a mixed solution including lipid, membrane proteins and the surfactant, wherein the content of the surfactant in the mixed solution is made equal to or more than the sum of a maximum amount of the surfactant associating with the lipid and a maximum amount of the surfactant associating with the membrane protein. | 05-27-2010 |
20100130382 | Liposome, Proteoliposome, Biochip, and Method for Producing Liposome and Proteoliposome - A liposome comprising a region of a lipid bilayer membrane with different membrane thicknesses, wherein each lipid bilayer membrane region is composed of a different lipid, and a thick membrane side in the region of the lipid bilayer membrane is formed of lipid having a phase transition temperature higher than that of the lipid forming a thin membrane side in the region of the lipid bilayer membrane. A proteoliposome, wherein the above-described liposome includes membrane proteins. A biochip, wherein the above-described liposome or the above-described proteoliposome is spread on a substrate. The above-described biochip, wherein the substrate includes at least one kind selected from the group consisting of mica, SiO | 05-27-2010 |
20110099673 | STAGE FOR SCANNING PROBE MICROSCOPY AND SAMPLE OBSERVATION METHOD - It is an object of the invention to provide a stage for scanning probe microscopy that can be used in any kind of SPM and can effectively irradiate light to a sample and a solution near the sample without irradiated light blocked by a cantilever. The stage for scanning probe microscopy of the invention is a stage for scanning probe microscopy for fixing a sample substrate that mounts a sample to be observed thereon and has optical transparency and includes an opening that is provided below a portion where the sample substrate is fixed and that has an opening area included within the sample substrate in plan view. Light is radiated from a bottom surface of the sample substrate onto the sample through the opening. | 04-28-2011 |
Patent application number | Description | Published |
20100169507 | Apparatus and method for managing subscription requests for a network interface component - In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a network interface component, and a management controller. The management controller may be configured to receive information related to a subscription request for a virtual machine, generate configuration information for the network interface component based on the subscription request, and provide the configuration information to the network interface component. Other embodiments are disclosed and claimed. | 07-01-2010 |
20120166891 | TWO-LEVEL SYSTEM MAIN MEMORY - Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. | 06-28-2012 |
20130268728 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES - A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space. | 10-10-2013 |
20130275682 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY OVER COMMON MEMORY CHANNELS - A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” | 10-17-2013 |
20130283079 | METHOD AND SYSTEM FOR PROVIDING INSTANT RESPONSES TO SLEEP STATE TRANSITIONS WITH NON-VOLATILE RANDOM ACCESS MEMORY - A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM. | 10-24-2013 |
20130318288 | METHOD AND SYSTEM FOR DATA DE-DUPLICATION - An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed. | 11-28-2013 |
20140006696 | APPARATUS AND METHOD FOR PHASE CHANGE MEMORY DRIFT MANAGEMENT | 01-02-2014 |
20140006848 | BAD BLOCK MANAGEMENT MECHANISM | 01-02-2014 |
20140040550 | MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS - A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol. | 02-06-2014 |
20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
20140129767 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY - A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” | 05-08-2014 |
20140281206 | Techniques for Probabilistic Dynamic Random Access Memory Row Repair - Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed. | 09-18-2014 |
20140304475 | DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY HIERARCHY - A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC. | 10-09-2014 |
20140317337 | METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) - Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed. | 10-23-2014 |
20140351660 | TWO-LEVEL SYSTEM MAIN MEMORY - Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. | 11-27-2014 |
20150089120 | REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY - Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed. | 03-26-2015 |
20150089245 | DATA STORAGE IN PERSISTENT MEMORY - Embodiments include systems, methods, and apparatuses associated with storing data in a persistent memory are disclosed herein. In embodiments, a memory controller may be configured to encrypt data with an encryption key, and the encrypted data may be stored in persistent memory. The memory controller may be further configured to alter and/or destroy the encryption key in response to a reset event. Other embodiments may be disclosed and/or claimed. | 03-26-2015 |
20150178202 | METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION - An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy. | 06-25-2015 |
20150378615 | ACCELERATING BOOT TIME ZEROING OF MEMORY BASED ON NON-VOLATILE MEMORY (NVM) TECHNOLOGY - Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed. | 12-31-2015 |
Patent application number | Description | Published |
20120265984 | NETWORK WITH PROTOCOL, PRIVACY PRESERVING SOURCE ATTRIBUTION AND ADMISSION CONTROL AND METHOD - A device implemented, carrier independent packet delivery universal addressing networking protocol for communication over a network between network nodes utilizing a packet. The protocol has an IP stack having layers. At least some of the layers have privacy preserving source node attribution and network admission control. The packet is admitted to the network only if a source node of the network nodes admits the packet. | 10-18-2012 |
20130108045 | METHODS, NETWORKS AND NODES FOR DYNAMICALLY ESTABLISHING ENCRYPTED COMMUNICATIONS | 05-02-2013 |
20130108050 | NETWORK HAVING MULTICAST SECURITY AND METHOD THEREFORE | 05-02-2013 |
20130170499 | BORDER GATEWAY BROKER, NETWORK AND METHOD - A device-implemented network with domains each having nodes, the nodes of each of the domains sharing network information with one another according to an intra-domain communication policy. An inter-domain protocol is configured to control communication between at least one of the nodes of one of the domains and at least one of the nodes of a different one of the domains. A broker is configured to be communicatively coupled to the nodes and configured to control communication according to the inter-domain protocol and to which all of the nodes of each of the plurality of domains are configured to send the network information. | 07-04-2013 |
20140372749 | NETWORK WITH PROTOCOL, PRIVACY PRESERVING SOURCE ATTRIBUTION AND ADMISSION CONTROL AND METHOD - A device implemented, carrier independent packet delivery universal addressing networking protocol for communication over a network between network nodes utilizing a packet. The protocol has an IP stack having layers. At least some of the layers have privacy preserving source node attribution and network admission control. The packet is admitted to the network only if a source node of the network nodes admits the packet. | 12-18-2014 |
20150257081 | HYBRID AUTONOMOUS NETWORK AND ROUTER FOR COMMUNICATION BETWEEN HETEROGENEOUS SUBNETS - A single routable network and an integrated router having a plurality of network interfaces for such network having a plurality of heterogeneous subnetworks having different network parameters, each of the plurality of network interfaces configured to be connected to a different one of the plurality of heterogeneous subnetworks. The integration router is configured to automatically connect with each of the plurality of heterogeneous subnetworks. The integration router providing persistent network connectivity between user nodes across the plurality of heterogeneous subnetworks | 09-10-2015 |