| Patent application number | Description | Published |
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| 20080261128 | Methods and structures for protecting one area while processing another area on a chip - Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. | 10-23-2008 |
| 20080272398 | CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING - A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide. | 11-06-2008 |
| 20090001466 | METHOD OF FORMING AN SOI SUBSTRATE CONTACT - A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening. | 01-01-2009 |
| 20090047756 | DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR - A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity. | 02-19-2009 |
| 20090079030 | Forming SOI Trench Memory with Single-Sided Buried Strap - A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench. | 03-26-2009 |
| 20090101995 | PROCESS FOR FABRICATION OF FINFETs - A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate. | 04-23-2009 |
| 20090148986 | METHOD OF MAKING A FINFET DEVICE STRUCTURE HAVING DUAL METAL AND HIGH-K GATES - A method of making a FinFET device structure, includes: providing a semiconductor-on-insulator (SOI) substrate having a semiconductor layer on an insulating layer on a base (e.g., semiconductor) layer; forming a cap layer (e.g., silicon nitride) on the SOI substrate; forming, on the insulating layer, first and second semiconductor fins with a first cap layer on the first fin and a second cap layer on the second fin; providing a first high-k dielectric layer across the first and the second cap layers and the first and second fins; providing a first metal layer onto the first high-k dielectric layer; providing a first semiconductor layer onto the first metal layer; removing the first semiconductor layer, the first metal layer, and the first high-k dielectric layer from the second cap layer, the second fin and from regions adjacent to the second fin; providing a second high-k dielectric layer onto the second cap layer, the second fin and a portion of the first metal layer; providing a second metal layer onto the second high-k dielectric layer, the second metal layer having a composition different than the first metal layer; providing a second semiconductor layer onto the second metal layer in a region above the second cap layer and into the regions adjacent to the second fin; removing the second semiconductor layer from the second metal layer in the region above the second cap layer, from adjoining regions and from the regions adjacent to the second fin; removing the second metal layer and the second high-k dielectric layer from a region above the first cap layer and from adjoining regions above the first semiconductor layer; removing the first metal layer, the first high-k dielectric layer, the first semiconductor layer, the second metal layer, the second high-k dielectric layer and the second semiconductor layer from regions above a plane containing top surfaces of the first and the second cap layers; forming first and second gates; forming respective source and drain regions within portions of the first and the second fins adjacent to the first and second gates, and then removing portions of the first and the second semiconductor layers, the first and the second high-k dielectric layers and the first and the second metal layers from a medial region between the first and the second fins. | 06-11-2009 |
| 20090159947 | SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION - The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides a design structure of the semiconductor structure, wherein the design structure is embodied in a machine readable medium. | 06-25-2009 |
| 20090176339 | Method of multi-port memory fabrication with parallel connected trench capacitors in a cell - A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage. | 07-09-2009 |
| 20090176347 | HYBRID ORIENTATION SUBSTRATE COMPATIBLE DEEP TRENCH CAPACITOR EMBEDDED DRAM - Method of limiting the lateral extent of a trench capacitor by a dielectric spacer in a hybrid orientations substrate is provided. The dielectric spacer separates a top semiconductor portion from an epitaxially regrown portion, which have different crystallographic orientations. The deep trench is formed as a substantially straight trench within the epitaxially regrown portion such that part of the epitaxially regrown portion remains overlying the dielectric spacer. The substantially straight trench is then laterally expanded to form a bottle shaped trench and to provide increased capacitance. The lateral expansion of the deep trench is self-limited by the dielectric spacer above the interface between the handle substrate and the buried insulator layer. During subsequent formation of a doped buried plate, the dielectric spacer blocks diffusion of dopants into the top semiconductor portion, providing a compact bottle shaped trench capacitor having high capacitance without introducing dopants into the top semiconductor portion. | 07-09-2009 |
| 20090200604 | VERTICAL FIN-FET MOS DEVICES - A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” ( | 08-13-2009 |
| 20090206442 | METHOD AND STRUCTURE FOR RELIEVING TRANSISTOR PERFORMANCE DEGRADATION DUE TO SHALLOW TRENCH ISOLATION INDUCED STRESS - A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate. | 08-20-2009 |
| 20100109049 | PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE - A device that includes a pattern of strained material and relaxed material on a substrate, a strained device in the strained material, and a non-strained device in the relaxed material. The strained material may be silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. Carbon-doped silicon or germanium-doped silicon may be used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon. | 05-06-2010 |
| 20100163949 | VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA - A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. | 07-01-2010 |
| 20100173449 | METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES - Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer. | 07-08-2010 |
| 20110092056 | ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT - Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate. | 04-21-2011 |
