Patent application number | Description | Published |
20080243443 | Method for the Construction of Vertical Power Transistors with Differing Powers by Combination of Pre-Defined Part Pieces - A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces. | 10-02-2008 |
20080265364 | Creation of Dielectrically Insulating Soi-Technlogical Trenches Comprising Rounded Edges for Allowing Higher Voltages - The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches ( | 10-30-2008 |
20080283960 | Production of a Carrier Wafer Contact in Trench Insulated Integrated Soi Circuits Having High-Voltage Components - The invention relates to a method for producing structures which make it possible to form a trench insulation and to bring into contact SOI wafers provided with active thick layers and which are easily processable. For this purpose, a carrier wafer electric contact and the insulation trench are provided with components exhibiting high-blocking capability of insertion into an integrated circuit SOI wafer. A narrow trench for an insulating trench ( | 11-20-2008 |
20080290366 | Soi Vertical Bipolar Power Component - An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping. | 11-27-2008 |
20080315346 | Passivation of Deep Isolating Separating Trenches with Sunk Covering Layers - Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches. | 12-25-2008 |
20090007046 | Layout Method for Vertical Power Transistors Having a Variable Channel Width - The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned. | 01-01-2009 |
20090090992 | ISOLATION TRENCH STRUCTURE FOR HIGH ELECTRIC STRENGTH - The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches ( | 04-09-2009 |
20090113362 | METHOD FOR DESIGNING A MASK FOR AN INTEGRATED CIRCUIT HAVING SEPARATE TESTING OF DESIGN RULES FOR DIFFERENT REGIONS OF A MASK PLANE - The invention relates to a method for designing integrated circuits, in particular a description and verification of design rules, wherein in one and the same process layer different design rules ( | 04-30-2009 |
20090294893 | ISOLATION TRENCH INTERSECTION STRUCTURE WITH REDUCED GAP WIDTH - The invention relates to isolation trenches having a high aspect ratio for trench-insulated smart power technologies in Silicon On Insulator (SOI) silicon wafers. The specific geometric layout of the intersections and junctions of the isolation trenches allows error rate reduction and simplification of manufacture. | 12-03-2009 |
20100295124 | MOS-POWER TRANSISTORS WITH EDGE TERMINATION WITH SMALL AREA REQUIREMENT - It is the purpose of the invention to provide a MOS transistor ( | 11-25-2010 |
20100308432 | SEMICONDUCTOR STRUCTURE FOR THE PRODUCTION OF A CARRIER WAFER CONTACT IN A TRENCH-INSULATED SOI DISK - Disclosed is a semiconductor structure for producing a handle wafer contact in trench insulated SOI discs which may be used as a deep contact ( | 12-09-2010 |
20110143519 | PRODUCTION OF ISOLATION TRENCHES WITH DIFFERENT SIDEWALL DOPINGS - A description is given of a method for producing isolation trenches ( | 06-16-2011 |
20110156093 | HIGH-VOLTAGE POWER TRANSISTOR USING SOI TECHNOLOGY - The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 μm. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT. | 06-30-2011 |
20120098084 | SEMICONDUCTOR COMPONENT WITH ISOLATION TRENCH INTERSECTIONS - A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area. | 04-26-2012 |
20120223367 | Method For Fabricating Semiconductor Wafers For The Integration of Silicon Components With Hemts, And Appropriate Semiconductor Layer Arrangement - The invention describes a method for fabricating silicon semiconductor waferswith the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafersare used, the active semiconductor layer of which has the III-V semiconductor layers ( | 09-06-2012 |
20120232855 | METHOD FOR THE CONSTRUCTION OF VERTICAL POWER TRANSISTORS WITH DIFFERING POWERS BY COMBINATION OF PRE-DEFINED PART PIECES - A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces. | 09-13-2012 |
20120270378 | Method for Producing Silicon Semiconductor Wafers Comprising a Layer for Integrating III-V Semiconductor Components - The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches ( | 10-25-2012 |
20120306010 | DMOS TRANSISTOR HAVING AN INCREASED BREAKDOWN VOLTAGE AND METHOD FOR PRODUCTION - A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material. | 12-06-2012 |