Patent application number | Description | Published |
20100088490 | METHODS AND SYSTEMS FOR MANAGING COMPUTATIONS ON A HYBRID COMPUTING PLATFORM INCLUDING A PARALLEL ACCELERATOR - In accordance with exemplary implementations, application computation operations and communications between operations on a host processing platform may be adapted to conform to the memory capacity of a parallel accelerator. Computation operations may be split and scheduled such that the computation operations fit within the memory capacity of the accelerator. Further, the operations may be automatically adapted without any modification to the code of an application. In addition, data transfers between a host processing platform and the parallel accelerator may be minimized in accordance with exemplary aspects of the present principles to improve processing performance. | 04-08-2010 |
20100088492 | SYSTEMS AND METHODS FOR IMPLEMENTING BEST-EFFORT PARALLEL COMPUTING FRAMEWORKS - Implementations of the present principles include Best-effort computing systems and methods. In accordance with various exemplary aspects of the present principles, a application computation requests directed to a processing platform may be intercepted and classified as either guaranteed computations or best-effort computations. Best-effort computations may be dropped to improve processing performance while minimally affecting the end result of application computations. In addition, interdependencies between best-effort computations may be relaxed to improve parallelism and processing speed while maintaining accuracy of computation results. | 04-08-2010 |
20120084747 | PARTITIONED ITERATIVE CONVERGANCE PROGRAMMING MODEL - Methods and systems for iterative convergence include performing at least one global iteration. Each global iteration includes partitioning input data into multiple input data partitions according to an input data partitioning function, partitioning a model into multiple model partitions according to a model partitioning function, performing at least one local iteration using a processor to compute sub-problems formed from a model partition and an input data partition to produce multiple locally updated models, and combining the locally updated models from the at least one local iteration according to a model merging function to produce a merged model. | 04-05-2012 |
20120131389 | CROSS-LAYER SYSTEM ARCHITECTURE DESIGN - Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference. | 05-24-2012 |
20130247194 | SECURING MEDICAL DEVICES THROUGH WIRELESS MONITORING AND ANOMALY DETECTION - A medical device monitor (MedMon), method and computer readable medium is disclosed. The MedMon is configured to operate in a system having communications between a first medical device associated with a patient and a second device. The MedMon includes a receiver configured to snoop on communications between the first medical device and second device. An anomaly detector having a set of security polices is configured to detect an anomaly by analyzing the communications between the first medical device and second device for compliance with the security policies. A response generator configured to generate a response on a condition that an anomaly is detected. The response may be a warning message configured to warn the patient. The MedMon may include a transmitter configured to transmit the response. The response may be a jamming signal configured to disrupt communications between the first medical device and second device. | 09-19-2013 |
20130298130 | AUTOMATIC PIPELINING FRAMEWORK FOR HETEROGENEOUS PARALLEL COMPUTING SYSTEMS - Systems and methods for automatic generation of software pipelines for heterogeneous parallel systems (AHP) include pipelining a program with one or more tasks on a parallel computing platform with one or more processing units and partitioning the program into pipeline stages, wherein each pipeline stage contains one or more tasks. The one or more tasks in the pipeline stages are scheduled onto the one or more processing units, and execution times of the one or more tasks in the pipeline stages are estimated. The above steps are repeated until a specified termination criterion is reached. | 11-07-2013 |
Patent application number | Description | Published |
20140052301 | Method for Globally Optimizing Power Flows in Electric Networks - A power flow problem (OPF) in an electric power network is globally optimized using a branch and bound tree of nodes connected by edges. The BB initially includes at least a root node, and each node represents a feasible region of limits on voltages and powers. An upper bound on the OPF problem is solved for selected nodes using nonlinear programming, while a lower bound is solved using a convex relaxation. The lowest upper and lower bounds are updated using the current upper and lower bound. If a difference between the lowest upper and lowest lower bound is less than a threshold, then outputting the voltages and the powers for the electric power network as represented by the feasibility region for the selected node. Otherwise, the feasible region of the node is partitioned to replace the node. The process is repeated until the tree is empty. | 02-20-2014 |
20150234780 | Optimal Parameter Selection and Acceleration in ADMM for Multi-stage Stochastic Convex Quadratic Programs - A method solves a stochastic quadratic program (StQP) for a convex set with a set of general linear equalities and inequalities by an alternating direction method of multipliers (ADMM). The method determines an optimal solution, or certifies that no solution exists. The method optimizes a step size β for the ADMM. The method is accelerated using a conjugate gradient (CG) method. The StMPC problem is decomposed into two blocks. The first block corresponds to an equality constrained QP, and the second block corresponds to a projection onto the StMPC inequalities and anticipativity constraints. The StMPC problem can be decomposed into a set of time step problems, and then iterated between the time step problems to solve the decoupled problems until convergence. | 08-20-2015 |
20160071013 | Method for Estimating Optimal Power Flows in Power Grids using Consensus-Based Distributed Processing - A method estimates an optimal power flows (OPF) in a power grid, which is represented as a graph partitioned into virtual sub-graphs, each including at least one bus, and associated with agents that measure local variables and updates consensus variables (CV). The consensus variables of adjacent virtual sub-graphs are exchanged and updated using the agents. An OPF problem is solved for the virtual sub-graphs using the agents based on the CV and the local variables. The exchanging and the solving are iterated until a termination condition is satisfied, when the optimal OPF is outputted for each virtual sub-graph. | 03-10-2016 |
Patent application number | Description | Published |
20140244059 | Method for Optimizing Power Flows in Electric Power Networks - Power flow in an electric power network is optimized during multiple time periods of operation of the electric power network by solving an optimization problem represented by an objective function by first initializing variables and constraints of a branch and bound (BB) tree, wherein nodes in the BB tree represent feasible regions of the optimization problem. Upper and lower bounds on the objective function are solved using the BB tree. A lowest upper bound and a lowest upper bound are updated. If difference between the lowest lower bound and the lowest upper bound is less than a threshold, the power flow is outputted based on the lowest lower bound and the lowest upper bound. | 08-28-2014 |
20140277858 | SYSTEM AND METHOD FOR OPTIMIZING ENERGY CONSUMPTION IN RAILWAY SYSTEMS - A method optimizes energy consumption in a railway system including a set of trains and a set of substations connected to a grid. The method optimizes control parameters controlling at least part of the energy consumption of the railway system to produce optimized control parameters minimizing a total power provided by the grid to satisfy a power demand of the railway system. The optimizing is subject to constraints on operations of the railway system, which include as complementarity constraint. Next, the method generates a command to control the energy consumption of the railway system based on the optimized control parameters. | 09-18-2014 |
20140277861 | System and Method for Optimizing Energy Consumption in Railway Systems with Energy Storage Devices - A system and method optimizes energy consumption in a railway system including a set of trains, a set of energy storage devices, and a set of substations connected to a grid by first optimizing control parameters controlling at least part of the energy consumption of the railway system to produce optimized control parameters. The optimized control parameters minimize, over multiple time steps, a combination of total power provided by the grid to satisfy a power demand of the railway system, a state-of-charge of each energy storage device, power supplied to charge the energy storage device and power supplied by the energy storage device. The optimizing is subject to constraints on operations of the railway system over multiple time steps. The constraints include a complementarity constraint. A command is generated to control the energy consumption of the railway system based on the optimized control parameters. | 09-18-2014 |
20140358508 | Method for Optimizing HVAC Systems in Buildings Using Nonlinear Programming to Maximize Comfort for Occupants - A heating, ventilation and air-conditioning (HVAC) system for a building is optimized while maximizing a comfort of occupants and minimizing energy consumption. The building is modeled as a network of nodes and edges, wherein the nodes represent rooms, and the edges represent walls. Dynamics of temperatures and humidity in the rooms and the temperature of the walls and the building are modeled using differential equations and the network. The comfort of the occupants is modeled by a predicted mean vote (PMV). The minimizing is formulated as an optimal control problem, which is discretized using an integration technique to obtain a finite dimensional optimization problem. Then, the finite dimensional optimization problem is solved using sparse linear algebra until convergence. | 12-04-2014 |
20150199606 | System and Method for Optimal Power Flow Analysis - A method determines a power flow of a power grid by optimizing an objective function representing an operation of the power grid using a spatial branch and bound (BB) framework for determining iteratively upper and lower bounds of the objective function. During the optimization, the lower bounds are determined using a semi-definite programming (SDP) relaxation of an optimal power flow (OPF) problem. | 07-16-2015 |
20150234779 | Method for Solving Quadratic Programs for Convex Sets with Linear Equalities by an Alternating Direction Method of Multipliers with Optimized Step Sizes - A method solves a convex quadratic program (QP) for a convex set. Constrains of the QP include sets of linear equalities and linear inequalities. The solving uses an Alternating Direction Method of Multipliers (ADMM). Variables of the convex QP include a linear subspace constrained variable vector and a set constrained variable vector. The method solves the linear subspace constrained variable vector while keeping the set constrained variable vector fixed using an optimal step size and a Lagrangian multiplier, and solves the set of constrained variable vector while keeping linear subspace constrained variable vector fixed using the optimal step size and the Lagrangian multiplier. Then, the Lagrangian multiplier is updated. A feasible solution is outputted if a termination condition for the feasible solution is satisfied, and an infeasible solution is signaled if a termination condition for the satisfied for the infeasible solution is satisfied. Otherwise, the steps are repeated. | 08-20-2015 |
20150370271 | Optimizing Operations of Multiple Air-Conditioning Units - A method operates a set of heating, ventilation and air-conditioning (HVAC) units by optimizing jointly operations of the set of HVAC units subject to constraints to determine times of switching each HVAC unit ON and OFF and by controlling each HVAC unit according to the corresponding times of switching. The operation of each HVAC unit is represented by a continuous function. The constraints include a complementarity constraint for each HVAC unit, such that the complementarity constraint for the HVAC unit defines a discontinuity of the operation of the HVAC unit at corresponding times of switching. | 12-24-2015 |
Patent application number | Description | Published |
20140274023 | App for Preventing Phone functionality while Driving - An app designed to prevent using distracting phone functionality, including texting, on a mobile phone while driving a vehicle is disclosed. The app first detects a speed at which the phone is travelling. If the speed is above a threshold, typically 5 mph the user is given a challenge that require either that both hands, or both eyes, are required on the phone. If the challenge is not met, the user is assumed to be the driver and the distracting phone functionality, including texting, is disabled. If the challenge is met, the user is assumed to be a passenger and the distracting phone functionality, including texting remains enabled. | 09-18-2014 |
20160044575 | System and Method for Preventing Phone Functionality while Driving - An app designed to prevent using distracting phone functionality, including texting, on a mobile phone while driving a vehicle is disclosed. The app detects and measure attributes including the phone's orientation and change of orientation and expresses them in a coordinate system relative to the direction of motion of the vehicle. If the phone orientation is found to be consistent with a change in direction of the vehicle, or the axis of rotation of the phone is found to be consistent with itself over time, the distracting phone functionality is disabled. | 02-11-2016 |
Patent application number | Description | Published |
20120221788 | MULTI-DIMENSIONAL ARRAY MANIPULATION - Method, system, and utility for performing an operation on data represented as elements of a multi-dimensional array. Operation on the data in the array may comprise performing a plurality of iterations. In each iteration, a plurality of elements in the array, stored contiguously in a first memory, may be selected based at least on a selected dimension of the array. The selected plurality of elements may be loaded into a second memory and a binary operator may be applied to each element of the selected plurality of elements and another element stored in the second memory. The second memory may have a smaller latency than the first memory. | 08-30-2012 |
20130080698 | GLOBAL DISTRIBUTED MEMORY RESHAPE OPERATIONS ON RANGE-PARTITIONED ARRAYS - Embodiments are directed to reshaping a partitioned data array. In an embodiment, a computer system identifies a block length parameter that describes the number of data blocks in the range-partitioned flattened representation of the array that appear consecutively in each locale. The computer system then identifies a stride parameter that describes the amount of separation between data blocks in the range-partitioned flattened representation of the array that appear consecutively in a plurality of locales. Based on the identified block length parameter and the stride parameter, the computer system determines which of the data blocks on the plurality of locales are to be sent to other locales to produce a local version of the reshaped array. The computer system then receives data blocks from the different locales in the distributed system and reconstructs the array based on the received blocks to create a local version of the reshaped array. | 03-28-2013 |
20130132783 | REPRESENTATION AND MANIPULATION OF ERRORS IN NUMERIC ARRAYS - In an embodiment, a computer system accesses various different data entries in dense data array, where at least one of those data entries in the dense data array is invalid. The computer system creates an associated sparse data array that includes multiple data entries with zero values as well as data entries with non-zero values. The non-zero data entries are configured to store location information and data values for each of the invalid data entries in the dense array. The zero-value data entries are inferred from the location information of the non-zero data entries. The computer system stores the location information and data values of the non-zero data entries in the sparse data array. Those data values stored in the sparse array are proportional to the number of invalid values in the dense array. | 05-23-2013 |
20130219226 | DISTRIBUTED TESTING WITHIN A SERIAL TESTING INFRASTRUCTURE - A serial testing infrastructure includes the capability to execute a distributed test on multiple virtual processors. A test executable may be stored in a library and the test description, including the name of the test, the test library, and other test characteristics, may be stored in a separate test data file. The serial testing infrastructure initiates multiple distributed test executors that each launch an instance of the distributed test as a process that runs concurrently with other instances of the distributed test. Each distributed test executor monitors execution of it corresponding process until completion or timeout. | 08-22-2013 |
20130297624 | Interoperability between Map-Reduce and Distributed Array Runtimes - Described is a technology by which Map-Reduce runtimes and distributed array runtimes are interoperable. Map-Reduce chunks are processed into array data for processing in a distributed array runtime based upon merge information. A staging Map-Reduce job tags a chunk with tag information that indicates a relative position of the chunk in an array. A distributed array framework imports files produced via a Map-Reduce framework and provides an array to an application of the distributed array framework for processing. An export mechanism may output one or more Map-Reduce files from the distributed array framework. | 11-07-2013 |
20130332907 | EXCEPTION HANDLING FOR A DISTRIBUTED RUNTIME - Embodiments are directed to handling errors in a distributed software application and to handling errors in a distributed software application. In one scenario, a computer system instantiates a distributed application which is configured for execution on multiple different computer systems. The computer system determines that an exception has occurred during the execution of the distributed application on at least one of the computer systems and translates the exception that occurred during distributed execution in a distributed environment into a serial exception that appears to have occurred during serial execution in a serial execution environment. The computer system then presents the translated serial exception to an application developer or other user. | 12-12-2013 |
20140006473 | PARTITIONED ARRAY OBJECTS IN A DISTRIBUTED RUNTIME | 01-02-2014 |
20140007060 | IMPLEMENTATION OF DISTRIBUTED METHODS THAT SUPPORT GENERIC FUNCTIONS | 01-02-2014 |
20140282614 | PROVIDING DISTRIBUTED ARRAY CONTAINERS FOR PROGRAMMING OBJECTS - Embodiments are directed to establishing registration objects for distributed processes, to managing memory on worker processes of a distributed software application and to using object serialization to communicate references to shim objects. In one scenario, a computer system accesses distributed process instances in a distributed runtime and creates a registration object for each of the process instances in the distributed runtime. The registration object includes a key value pair, where the key includes a unique identifier (ID) that identifies a distributed array instance associated with the distributed process, and the value includes a reference to a local portion of the distributed array instance. The computer system then maintains a mapping between the unique ID and the distributed array instance using the registration object. As such, the key value refers to the local portion of the same distributed array instance on each distributed process of the distributed runtime. | 09-18-2014 |
20140372495 | SINGULAR VALUE DECOMPOSITION OF COMPLEX MATRIX - Computerized singular value decomposition of an input complex matrix. A real-value matrix representation of the input complex matrix is provided to a singular value decomposition module, which correctly obtains a singular value representation of the real-value matrix representation. However, the result is not provided in a form for convenient conversion back into a valid singular value decomposition solution for the original input complex matrix, as the upper left half and lower right half of the diagonal of the diagonal matrix are not identical. A correction module corrects by formulating a corrected diagonal matrix that represents the value of the diagonal of the first diagonal matrix, but shuffled so that the upper left half of the diagonal of the second diagonal matrix is the same as the lower right half of the diagonal of the second diagonal matrix. Corrected unitary matrices may also be formed. | 12-18-2014 |
20150040141 | PROVIDING DISTRIBUTED ARRAY CONTAINERS FOR PROGRAMMING OBJECTS - Embodiments are directed to establishing registration objects for distributed processes, to managing memory on worker processes of a distributed software application and to using object serialization to communicate references to shim objects. In one scenario, a computer system accesses distributed process instances in a distributed runtime and creates a registration object for each of the process instances in the distributed runtime. The registration object includes a key value pair, where the key includes a unique identifier (ID) that identifies a distributed array instance associated with the distributed process, and the value includes a reference to a local portion of the distributed array instance. The computer system then maintains a mapping between the unique ID and the distributed array instance using the registration object. As such, the key value refers to the local portion of the same distributed array instance on each distributed process of the distributed runtime. | 02-05-2015 |
20150317334 | SPARSE DATATABLE DATA STRUCTURE - A sparse dataset structure is created by creating column vectors for one or more columns in a dataset that have at least one significant value. Each column vector includes data values for columns of the dataset. Each column vector that is a sparse column vector includes a look-up index array and a value array. Entries in the look-up index array represent columns. The value array includes values for a row in a column. Each entry in the value array points to a row entry in the look-up index array. A side structure includes a row index and a column index. The row index includes a location for an entry for each row where entries point to a location in the column index that identifies a column that has a first significant entry for a row. Alternatively a sparse dataset could be constructed with sparse rows. | 11-05-2015 |
Patent application number | Description | Published |
20140252660 | MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES - Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers. | 09-11-2014 |
20140272677 | METHODS FOR FABRICATING EUV MASKS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH EUV MASKS - A method for fabricating integrated circuits includes fabricating an EUV mask by providing a photomask having a border region. A photoresist is formed over the photomask and has a border region overlying the border region of the photomask. The method exposes an inner portion and an outer portion of the photoresist border region. The method removes the inner portion and the outer portion to expose the border region of the photomask. The border region of the photomask is etched using the photoresist as a mask to form the EUV mask with a non-reflective border. The photoresist is removed from the EUV mask. The method includes forming another photoresist over a partially-fabricated integrated circuit layer and patterning the photoresist by exposure to EUV light reflected from the EUV mask to expose portions of the partially-fabricated integrated circuit layer. Portions of the partially-fabricated integrated circuit layer and the photoresist are removed. | 09-18-2014 |
20140273306 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING MULTI-PATTERNING OF MASKS FOR EXTREME ULTRAVIOLET LITHOGRAPHY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask. | 09-18-2014 |
Patent application number | Description | Published |
20140090879 | EMBEDDED ARCHITECTURE USING RESIN COATED COPPER - Electronic assemblies and methods for their manufacture are described, including those related to the formation of an assembly including a carrier and a resin coated copper layer positioned on the carrier. The resin coated copper layer includes a first layer comprising a resin and a second layer comprising copper, with the first layer bonded to the second layer. The first layer of the resin coated copper is positioned between the carrier and the second layer of the resin coated copper. An opening is formed in the second layer of the resin coated copper. A die is positioned in the opening. A plurality of dielectric layers and metal pathways are positioned on the second layer and on the die. Other embodiments are described and claimed. | 04-03-2014 |
20140091469 | METHODS OF PROVIDING DIELECTRIC TO CONDUCTOR ADHESION IN PACKAGE STRUCTURES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material. | 04-03-2014 |
20140093999 | EMBEDDED STRUCTURES FOR PACKAGE-ON-PACKAGE ARCHITECTURE - Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed. | 04-03-2014 |
20150014861 | EMBEDDED STRUCTURES FOR PACKAGE-ON-PACKAGE ARCHITECTURE - Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed. | 01-15-2015 |
20150357185 | METHODS OF PROVIDING DIELECTRIC TO CONDUCTOR ADHESION IN PACKAGE STRUCTURES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material. | 12-10-2015 |