Patent application number | Description | Published |
20080237719 | Multi-gate structure and method of doping same - A multi-gate structure includes a substrate ( | 10-02-2008 |
20090020792 | ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE - A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours. | 01-22-2009 |
20090061572 | NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION - A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 03-05-2009 |
20100059821 | Isolated tri-gate transistor fabricated on bulk substrate - A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours. | 03-11-2010 |
20110020987 | NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION - A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 01-27-2011 |
20120138886 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 06-07-2012 |
20120161202 | JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 06-28-2012 |
20130313513 | SEMICONDUCTOR DEVICES HAVING MODULATED NANOWIRE COUNTS - Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes. | 11-28-2013 |
20130320448 | SEMICONDUCTOR DEVICES HAVING THREE-DIMENSIONAL BODIES WITH MODULATED HEIGHTS - Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different. | 12-05-2013 |
20130320455 | SEMICONDUCTOR DEVICE WITH ISOLATED BODY PORTION - Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body. | 12-05-2013 |
20130334572 | JUNCTIONLESS ACCUMULATION-MODE DEVICES ON DECOUPLED PROMINENT ARCHITECTURES - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 12-19-2013 |
20140001441 | INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES | 01-02-2014 |
20140001560 | ISOLATED AND BULK SEMICONDUCTOR DEVICES FORMED ON A SAME BULK SUBSTRATE | 01-02-2014 |
20140035059 | SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS - Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region. | 02-06-2014 |
20140042386 | NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS - Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires. | 02-13-2014 |
20140138744 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion. | 05-22-2014 |
20140197377 | CMOS NANOWIRE STRUCTURE - Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire. | 07-17-2014 |
20140262707 | NANOWIRE-BASED MECHANICAL SWITCHING DEVICE - Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire. | 09-18-2014 |
20140264253 | LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS - A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors. | 09-18-2014 |
20140326952 | SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES - Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other. | 11-06-2014 |
20150021553 | JUNCTIONLESS ACCUMULATION-MODE DEVICE ISOLATED FROM SEMICONDUCTIVE SUBSTRATE BY REVERSE-BIAS JUNCTION - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 01-22-2015 |
20150041847 | TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS - Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion. | 02-12-2015 |