Patent application number | Description | Published |
20080248596 | Method of making a circuitized substrate having at least one capacitor therein - A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels. | 10-09-2008 |
20100060381 | Mulit-layer embedded capacitance and resistance substrate core - A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser. | 03-11-2010 |
20100167210 | MULTI-LAYER EMBEDDED CAPACITANCE AND RESISTANCE SUBSTRATE CORE - A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser. | 07-01-2010 |
20110039212 | Circuitized substrate with internal resistor, method of making said circuitized substrate, and electrical assembly utilizing said circuitized substrate - A circuitized substrate which utilizes at least one internal (embedded) resistor as part thereof, the resistor comprised of a material including resin and a quantity of powders of nano-particle and/or micro-particle sizes. The resistor serves to decrease the capacitance in the formed circuit while only slightly increasing the high frequency resistance, thereby improving circuit performance through the substantial elimination of some discontinuities known to exist in structures like these. An electrical assembly (substrate and at least one electrical component) is also provided. | 02-17-2011 |
20110043987 | METHOD OF MAKING CIRCUITIZED SUBSTRATE WITH RESISTOR INCLUDING MATERIAL WITH METAL COMPONENT AND ELECTRICAL ASSEMBLY AND INFORMATION HANDLING SYSTEM UTILIZING SAID CIRCUITIZED SUBSTRATE - A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided. | 02-24-2011 |
20120015532 | HIGH DENSITY DECAL AND METHOD FOR ATTACHING SAME - A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal. | 01-19-2012 |
20120017437 | CIRCUITIZED SUBSTRATE WITH CONDUCTIVE PASTE, ELECTRICAL ASSEMBLY INCLUDING SAID CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAID SUBSTRATE - A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto. | 01-26-2012 |
20120031649 | CORELESS LAYER BUILDUP STRUCTURE WITH LGA AND JOINING LAYER - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging. | 02-09-2012 |
20120068326 | ANTI-TAMPER MICROCHIP PACKAGE BASED ON THERMAL NANOFLUIDS OR FLUIDS - A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling. | 03-22-2012 |
20120069531 | CONDUCTING PASTE FOR DEVICE LEVEL INTERCONNECTS - A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance. | 03-22-2012 |
20120152605 | CIRCUITIZED SUBSTRATE WITH DIELECTRIC INTERPOSER ASSEMBLY AND METHOD - A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed. | 06-21-2012 |
20120160544 | CORELESS LAYER BUILDUP STRUCTURE WITH LGA - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging. | 06-28-2012 |
20120160547 | CORELESS LAYER BUILDUP STRUCTURE - A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. | 06-28-2012 |
20120162928 | ELECTRONIC PACKAGE AND METHOD OF MAKING SAME - An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates and also including an opening therein in which is positioned at least one electrical component, such as a semiconductor chip, coupled to the lower or base substrate. A second component may also be mounted on and electrically coupled to the upper surface of the top or cover circuitized substrate. A method of making such a package is also provided. | 06-28-2012 |
20120201006 | ELECTRONIC PACKAGE WITH THERMAL INTERPOSER AND METHOD OF MAKING SAME - An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package. | 08-09-2012 |
20120223047 | METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE - Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces. | 09-06-2012 |
20120228014 | CIRCUITIZED SUBSTRATE WITH INTERNAL THIN FILM CAPACITOR AND METHOD OF MAKING SAME - A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided. | 09-13-2012 |
20120243155 | CONDUCTIVE METAL NUB FOR ENHANCED ELECTRICAL INTERCONNECTION, AND INFORMATION HANDLING SYSTEM UTILIZING SAME - A method of forming a circuitized substrate utilizing a conductive nub structure for enhanced interconnection integrity by using a joining core layer with copper outer layer on it, and forming thru-holes in the joining layer. Placing conductive adhesive in the thru-hole prior to removing the copper outer layers from the joining core layer creates an adhesive bump on joining core layer that engages a conductive secondary metal nub placed on the circuitized substrate-to-joining layer contact points, thus creating an enhanced connection between the layers. | 09-27-2012 |
20120257343 | CONDUCTIVE METAL MICRO-PILLARS FOR ENHANCED ELECTRICAL INTERCONNECTION - A method of forming a circuitized substrate for use in electronic packages. A substrate layer is provided that has a copper pad on a surface. A conductive seed layer and a photoresist layer are placed on the surface. The photoresist is developed and conductive material is placed within the developed features and a second conductive material placed on the first conductive material. The photoresist and conductive seed layer are removed to leave a micro-pillar array. The joining and lamination of two circuitized substrate layers utilizes the micro-pillar array for the electrical connection of the circuitized substrate layers. | 10-11-2012 |
20130033827 | ELECTRICALLY CONDUCTIVE ADHESIVE (ECA) FOR MULTILAYER DEVICE INTERCONNECTS - A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling. | 02-07-2013 |