Patent application number | Description | Published |
20110309504 | STACK PACKAGE - A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines. | 12-22-2011 |
20120091584 | BUMP FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE HAVING BUMP, AND STACKED SEMICONDUCTOR PACKAGE - A bump for a semiconductor package includes: a first bump formed on a semiconductor chip and having at least two land parts and a connection part which connects the land parts and has a line width smaller than the land parts; and a second bump formed on the first bump and projecting on the land parts of the first bump in shapes of a hemisphere. | 04-19-2012 |
20120112342 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor device includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first electrode pads on the first surface, a stress buffer layer formed on the first electrode pads and the first surface of the first structural body, and having a plurality of holes which expose the first electrode pads, and a plurality of bumps formed to be electrically connected with the first electrode pads through the plurality of holes, wherein the plurality of bumps include first bumps which are filled in corresponding holes of the plurality of holes and second bumps which are formed on the first bumps and the stress buffer layer and are disposed over the first electrode pads and portions of the first surface outside the first electrode pads. | 05-10-2012 |
20130037938 | EMBEDDED PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to is the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump. | 02-14-2013 |
20130334683 | ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURING THE SAME - An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip. | 12-19-2013 |
20130334685 | EMBEDDED PACKAGES AND METHODS OF MANUFACTURING THE SAME - An embedded package that may be realized by surrounding a semiconductor chip (or a semiconductor die) in a package substrate. A semiconductor chip of an embedded package may be electrically connected to external connection terminals through interconnection wires instead of bumps, and the interconnection wires may be formed using a wire bonding process. A high reliability embedded package results. | 12-19-2013 |
20140175680 | ELECTRICAL CHARACTERISTICS OF PACKAGE SUBSTRATES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided. | 06-26-2014 |
20140291837 | EMBEDDED PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the to semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump. | 10-02-2014 |
20140367851 | EMBEDDED PACKAGES, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - Embedded packages are provided. The embedded package includes a chip attached to a first surface of a core layer, a plurality of bumps on a surface of the chip opposite to the core layer, and a first insulation layer surrounding the core layer, the chip and the plurality of bumps. The first insulation layer has a trench disposed in a portion of the first insulation layer to expose the plurality of bumps. | 12-18-2014 |
20150056755 | ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURING THE SAME - An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip. | 02-26-2015 |