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Qureshi, US

Adnan Igbal Qureshi, Edina, MN US

Patent application numberDescriptionPublished
20120220983EXTERNAL LOOP FOR EXCHANGING CATHETERS AND DELIVERY DEVICES OVER EXCHANGE LENGTH WIRES DURING CATHETER BASED PROCEDURES - A method and device for exchanging catheters and microcatheters over exchange length wires is disclosed. The device consists of a hollow tube in a loop configuration attached to a base in which the extracorporeal segment of an exchange-length guidewire is inserted. The superior aspect of the tubular loop has a longitudinal slit which allows to and fro movement of catheters using a catheter holder having a handle that protrudes through the slit for easy manipulation.08-30-2012

Adnan Iqbal Qureshi, Minneapolis, MN US

Patent application numberDescriptionPublished
20120253266Extradural Infusion Suction System and Method to Drain Fluid Collection in the Extradural Space of Spinal Cord - A minimally invasive method of and apparatus for aspirating purulent material from an epidural abscess, or the like, in a patient includes a dual concentric catheter system having an inner infusion catheter and an outer suction catheter, the infusion catheter able to be advanced relative to and beyond the suction catheter. The catheter system is introduced into the extradural space through percutaneous entry and advanced to an epidural abscess of interest. Infusion is used to dislodge purulent material ahead of the infusion catheter toward side openings in the suction catheter where it is aspirated.10-04-2012

Adnan Iqbal Qureshi, Edina, MN US

Patent application numberDescriptionPublished
20110264217Intraspinal Device Deployed Through Percutaneous Approach Into Subarachnoid or Intradural Space of Vertebral Canal to Protect Spinal Cord From External Compression - To shield the spinal cord from an external compression, a barrier device having a self-expanding frame and covered with a non-porous elastomeric sheet is routed through either the subarachnoid or intradural space to the site of the compression through the lumen of a delivery catheter that is percutaneously inserted using an introducer needle. When the distal end of the delivery catheter is proximate the site of the compression, the barrier device is pushed out the distal end of the catheter and allowed to self-expand so as to be interposed between the compression and the spinal cord to prevent impingement.10-27-2011

Ahmed I. Qureshi US

Patent application numberDescriptionPublished
20120084227System and Method for Mapping and Compliance Monitoring of Banks - A system and method for creating and maintaining a correspondent banking relationship mapping including current illicit designations. The system enables identification of a bank's correspondent relationships and the relationships of their correspondents. Through the system and method users can identify which banks have illicit relationships prior to engaging with banks or can be notified if the status of any banks which they have an existing relationships changes because a correspondent bank has entered into a correspondent relationship with an illicit banking entity.04-05-2012

Azhar Qureshi, Whitinsville, MA US

Patent application numberDescriptionPublished
20080295686Method and apparatus for removing contaminants from a reflow apparatus - A reflow apparatus for solder joining electronic components to a substrate includes a reflow chamber, a conveyor to convey a substrate within the chamber, at least one heating element to provide heat to reflow solder on the substrate, and at least one system to remove contaminants generated from the reflow solder. The system is coupled with the chamber for passage of a vapor stream from the chamber through the system. The system comprises a contaminant collection unit in fluid communication with the vapor stream. The contaminant collection unit includes a coil and a collection container. The coil is configured to receive cooled gas therein. The arrangement is such that when introducing cooled gas in the coil, contaminants in the vapor stream condense on the coil, and when ceasing the introduction of cooled gas in the coil, contaminants in the vapor stream are released from the coil and collected in the collection container. Other embodiments and methods for removing contaminants are further disclosed.12-04-2008
20110272451METHOD AND APPARATUS FOR REMOVING CONTAMINANTS FROM A REFLOW APPARATUS - A reflow apparatus for solder joining electronic components to a substrate includes a reflow chamber, a conveyor to convey a substrate within the chamber, at least one heating element to provide heat to reflow solder on the substrate, and at least one system to remove contaminants generated from the reflow solder. The system is coupled with the chamber for passage of a vapor stream from the chamber through the system. The system comprises a contaminant collection unit in fluid communication with the vapor stream. The contaminant collection unit includes a coil and a collection container. The coil is configured to receive cooled gas therein. The arrangement is such that when introducing cooled gas in the coil, contaminants in the vapor stream condense on the coil, and when ceasing the introduction of cooled gas in the coil, contaminants in the vapor stream are released from the coil and collected in the collection container. Other embodiments and methods for removing contaminants are further disclosed.11-10-2011

Imran Qureshi, Austin, TX US

Patent application numberDescriptionPublished
20110058641FAST DYNAMIC REGISTER - A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.03-10-2011

Patent applications by Imran Qureshi, Austin, TX US

Khalid Qureshi, Mason, OH US

Patent application numberDescriptionPublished
20090127742Process For Activating A Web - A process for simultaneously activating two or more portions of a web in different directions. The process involves feeding a web into an apparatus that includes a pair of intermeshing activation rolls having three dimensional surface features configured to simultaneously activate different portions a web in different directions. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation.05-21-2009
20090130242Apparatus For Activating A Web - An apparatus for simultaneously activating two or more portions of a web in different directions. The apparatus includes a pair of intermeshing activation rolls with three-dimensional surface features disposed thereon. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation.05-21-2009
20090131901Outer Cover For A Disposable Absorbent Article - An outer cover for a disposable absorbent article. The outer cover includes an elastic material joined to an extensible material to form a laminate. At least two different areas of the laminate are simultaneously activated in different directions by a single pair of intermeshing activation rolls. At least a portion of the two different areas of activation on the outer cover are spatially separated by a buffer zone.05-21-2009
20100228212Outer Cover for a Disposable Absorbent Article - An outer cover for a disposable absorbent article including waist regions elastically stretchable in the cross machine direction and activated in the cross machine direction, activated leg cuff regions elastically stretchable in one or more directions other than the cross machine direction, and an inelastic crotch region having a nonwoven crotch patch for providing the outer cover with suitable tensile strength, opacity, and poke-through properties.09-09-2010
20110024940Method For Making An Elastomeric Apertured Web - A method for making an elastomeric apertured web comprises providing a precursor web comprising a laminate which is subjected to incremental stretching to form an elastomeric precursor web. A forming apparatus is provided comprising a first member and a second member, wherein the first member comprises a mating member, and the second member comprises teeth which are joined to the second member. The elastomeric precursor web is moved through the forming apparatus, wherein apertures are formed in the elastomeric precursor web material as the teeth on the second member penetrate the mating member forming an elastomeric apertured web. The elastomeric apertured web exhibits a WVTR of at least about 1000 g/m02-03-2011
20110031649Process for Activating A Web - A process for simultaneously activating two or more portions of a web in different directions. The process involves feeding a web into an apparatus that includes a pair of intermeshing activation rolls having three dimensional surface features configured to simultaneously activate different portions a web in different directions. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation.02-10-2011
20110117235Apparatus For Activating A Web - An apparatus for simultaneously activating two or more portions of a web in different directions. The apparatus includes a pair of intermeshing activation rolls with three-dimensional surface features disposed thereon. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation.05-19-2011
20110208486COMPUTER BASED MODELING OF FIBROUS MATERIALS - Computer based models of fibrous materials.08-25-2011
20110208487COMPUTER BASED MODELING OF PROCESSED FIBROUS MATERIALS - Computer based models of processed fibrous materials.08-25-2011
20110250413BOND PATTERNS FOR FIBROUS WEBS - Bond patterns for fibrous webs.10-13-2011
20120032370Process For Activating A Web - A process for simultaneously activating two or more portions of a web in different directions. The process involves feeding a web into an apparatus that includes a pair of intermeshing activation rolls having three dimensional surface features configured to simultaneously activate different portions a web in different directions. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation.02-09-2012

Patent applications by Khalid Qureshi, Mason, OH US

Moinuddin Qureshi, White Plains, NY US

Patent application numberDescriptionPublished
20110252215COMPUTER MEMORY WITH DYNAMIC CELL DENSITY - A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region.10-13-2011

Moinuddin K. Qureshi, Austin, TX US

Patent application numberDescriptionPublished
20090006742Method and apparatus improving performance of a digital memory array device - A method for improving performance of a digital memory array device including a plurality of memory cells; each respective memory cell storing a first digital value and a second digital value being an inverse of the first digital value; storing of the first and second digital values being controlled by a first digital signal effecting selection of a specified memory cell for storing; includes: (a) determining an extant value relating to the first digital signal; (b) if the extant value has a first value, effecting a bit flip operation in the specified memory cell to invert values of at least one of the stored first digital and the second digital values; (c) if the extant value does not have the first value, foregoing the bit flip operation in the specified memory cell.01-01-2009

Moinuddin K. Qureshi, Yorktown Heights, NY US

Patent application numberDescriptionPublished
20110026318ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS - Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.02-03-2011

Moinuddin K. Qureshi, White Plains, NY US

Patent application numberDescriptionPublished
20100030970Adaptive Spill-Receive Mechanism for Lateral Caches - Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates that a plurality of non-dedicated cache sets within the cache should operate as spill cache sets or receive cache sets. The cache controller sets the plurality of non-dedicated cache sets to spill an evicted cache line to an associated cache set in another cache in the event of a cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the spill cache sets. The cache controller sets the plurality of non-dedicated cache sets to receive an evicted cache line from another cache set in the event of the cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the receive cache sets.02-04-2010
20110078382Adaptive Linesize in a Cache - A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.03-31-2011
20110078412Processor Core Stacking for Efficient Collaboration - A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores.03-31-2011
20120030481Measuring Data Switching Activity in a Microprocessor - A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.02-02-2012
20120131304Adaptive Wear Leveling via Monitoring the Properties of Memory Reference Stream - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.05-24-2012

Patent applications by Moinuddin K. Qureshi, White Plains, NY US

Moinuddin Khalil Ahmed Qureshi, Austin, TX US

Patent application numberDescriptionPublished
20080215816APPARATUS AND METHOD FOR FILTERING UNUSED SUB-BLOCKS IN CACHE MEMORIES - A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.09-04-2008

Patent applications by Moinuddin Khalil Ahmed Qureshi, Austin, TX US

Moinuddin Khalil Ahmed Qureshi, White Plains, NY US

Patent application numberDescriptionPublished
20110055515REDUCING BROADCASTS IN MULTIPROCESSORS - Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.03-03-2011
20110191546MEMORY ACCESS PREDICTION - An apparatus for memory access prediction which includes a plurality of processors, a plurality of memory caches associated with the processors, a plurality of saturation counters associated with the processors, each of the saturation counters having an indicator bit, and a physical memory shared with the processors, saturation counters and memory caches. Upon a cache miss for a data item, a cache snoop and access to physical memory are initiated in parallel for the data item if the indicator bit is a first predetermined bit (one (1) or zero (0)) whereas a cache snoop is initiated if the most significant bit is a second predetermined bit (zero (0) or one (1)).08-04-2011

Nasibuddin Qureshi, Morton, IL US

Patent application numberDescriptionPublished
20090162912PROCESS FOR CONTINUOUS SOLVENT PRODUCTION - A continuous process for production of solvents, particularly acetone-butanol-ethanol (ABE) using fermentation of solventogenic microorganisms and gas stripping is provided. The solventogenic microorganisms are inoculated in a nutrient medium containing assimilable carbohydrates (substrate) and optional other additives. Control of the solventogenic microorganism concentration in the fermentor (cell concentration) and the assimilable carbohydrate concentration in the fermentor, along with removal of solvents formed results in a continuous process for production of solvents.06-25-2009

Qadeer A. Qureshi, Dripping Springs, TX US

Patent application numberDescriptionPublished
20090016140DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY - A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.01-15-2009

Patent applications by Qadeer A. Qureshi, Dripping Springs, TX US

Rashid Qureshi, Redmond, WA US

Patent application numberDescriptionPublished
20100138501END-TO-END VALIDATION IN A PUSH ENVIRONMENT - In a push environment having a communication path along which a service provides messages to a computing device via a gateway, an inactivity timeout value and a registration timeout value enable the computing device to detect failures in the communication path. An application executing on the computing device registers an application endpoint with the gateway. The application separately subscribes to the service to receive the messages. If there is inactivity in accordance with the inactivity timeout value, the application de-registers and re-registers with the gateway, and unsubscribes and re-subscribes with the service.06-03-2010
20110145063TARGETING APPLICATIONS WITH ADVERTISEMENTS - Collecting application execution data by a push service and targeting application programs with advertisements based on the collected data. Statistics such as activity, popularity, and frequency of execution for each of the application programs are generated based on the collected data. The statistics are matched to advertising campaigns to select application programs relevant to the advertising campaigns. Advertisers are charged for delivering the advertisements based on the selected application programs. For example, advertisements delivered to frequently executed application programs are more expensive than advertisements delivered to application programs that are rarely executed.06-16-2011
20110173681 FLEXIBLE AUTHENTICATION AND AUTHORIZATION MECHANISM - Techniques and tools for flexible authentication and authorization of services on a push framework. For example, a push notification framework allows services (social networking web services, etc.) to use either an authenticated access mode or an unauthenticated access mode, in order to push information to client devices (e.g., mobile devices). In the authenticated mode, the push framework requires registration of the service with the push framework before allowing the service to push notifications to client devices. Different authenticated modes are provided for third-party and first-party services. In the unauthenticated mode, registration is not required, but notifications are throttled, thereby limiting risk of abuse by unauthenticated services. This allows flexibility for services that use the push framework.07-14-2011
20120198268RE-ESTABLISHING PUSH NOTIFICATION CHANNELS VIA USER IDENTIFIERS - Embodiments enable recovery of push notification channels via session information associated with user identifiers. A proxy service creates session information describing push notification channels (e.g., subscriptions) for a user and associates the session information with a user identifier. The session information is stored in a cloud service or other storage area separate from the proxy service. After failure of a user computing device or the proxy service, the session information is obtained via the user identifiers and the push notification channels are re-created with the session information. In some embodiments, the proxy service enables delivery of the same notification to multiple computing devices associated with the user identifier.08-02-2012

Patent applications by Rashid Qureshi, Redmond, WA US

Rauf A. Qureshi, Marietta, GA US

Patent application numberDescriptionPublished
20090041211Wireless and Wireline Messaging Services - Automatic access to a secondary or alternate voicemail box while operating or using a first or primary voicemail box is provided. One touch access to an alternate voicemail box from a wireless telephone device is further provided, and access to a given voicemail box from a number of trusted telephone devices is provided without requiring users of the trusted devices to authenticate into the voicemail box (e.g., provide a password).02-12-2009

Shahid P. Qureshi, Duluth, GA US

Patent application numberDescriptionPublished
20080293911ANHYDRIDE AND RESORCINOL LATENT CATALYST SYSTEM FOR IMPROVING CURE CHARACTERISTICS OF PHENOLIC RESINS - An anhydride and resorcinol latent catalyst system for a phenolic resole resin provides a resin having long pot life and long shelf life, yet cures quickly thereafter.11-27-2008