Patent application number | Description | Published |
20080314878 | APPARATUS AND METHOD FOR CONTROLLING A MACHINING SYSTEM - An apparatus for controlling a machining system is provided. The apparatus include an optical unit configured to capture an image of an object based upon radiation generated from the object and an image processing unit configured to process the image and to obtain real-time estimation of parameters associated with manufacture or repair of the object. The apparatus also includes a process model configured to establish target values for the parameters associated with the manufacture or repair of the object based upon process parameters for the machining system and a controller configured to control the process parameters for the machining system based upon the estimated and target values of the parameters associated with the manufacture or repair of the object. | 12-25-2008 |
20100140236 | LASER MACHINING SYSTEM AND METHOD - A laser machining system comprises a laser configured to generate a laser output for forming a molten pool on a substrate, a nozzle configured to supply a growth material to the molten pool for depositing the material on the substrate, and an optical unit configured to capture a plurality of grayscale images comprising temperature data during the laser deposition process, wherein the grayscale images correspond to respective ones of a plurality of radiation beams with different desired wavelengths. Further, the laser machining system comprises an image-processing unit configured to process the grayscale images to retrieve the temperature data according to linear relationships between temperatures in the laser deposition process and the corresponding grayscales of the respective images. A laser machining method is also presented. | 06-10-2010 |
20100200189 | METHOD OF FABRICATING TURBINE AIRFOILS AND TIP STRUCTURES THEREFOR - A method for making a turbine airfoil includes providing a mold core and an outer shell which cooperatively define a cavity in the shape of a hollow airfoil having an outer wall, a root, and a tip. A tip portion of the core extends completely through the portion of the cavity defining the tip of the airfoil. The core is restrained to prevent movement between the core and outer shell. Molten metal is introduced into the cavity and solidified to form an airfoil having at least one outer wall which defines an open tip and a hollow interior. A metallic tip cap is formed on the outer wall which substantially closes off the open tip. The tip cap may be formed by packing the airfoil with metallic powder; and laser sintering the exposed powder so as to form a tip cap which is metallurgically bonded to the outer wall. | 08-12-2010 |
20110168679 | METHODS FOR TREATING SUPERALLOY ARTICLES, AND RELATED REPAIR PROCESSES - A method is described, for treating a superalloy substrate which includes at least one cavity containing adherent metal oxide material on its surface. A short-pulsed, high repetition rate laser beam is directed against the cavity surface for a period of time sufficient to remove substantially all of the adherent metal oxide material. The laser beam is characterized by a peak power density in the range of about 10 megawatts/cm | 07-14-2011 |
Patent application number | Description | Published |
20080209373 | METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS - Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability. | 08-28-2008 |
20080209374 | Parameter Ordering For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion. | 08-28-2008 |
20080209375 | Variable Threshold System and Method For Multi-Corner Static Timing Analysis - A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. | 08-28-2008 |
20120124534 | System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times - A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack. | 05-17-2012 |
20120311515 | Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs - A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together. | 12-06-2012 |
Patent application number | Description | Published |
20140044889 | METHODS OF MAKING STRESSED MATERIAL LAYERS AND A SYSTEM FOR FORMING SUCH LAYERS - Disclosed herein are various methods of making stressed material layers and a system for forming such layers. In one example, a deposition/irradiation system disclosed herein includes a process chamber, a wafer stage positioned within the process chamber, a deposition region and an irradiation region within the process chamber, wherein the system is adapted to separate the deposition region and the irradiation region by generating at least one isolating gas region between the deposition region and the irradiation region, means for supplying a precursor gas to the deposition region, means for supplying ultraviolet radiation to the irradiation region and means for supplying an isolation gas to the at least one isolating gas region. | 02-13-2014 |
20140070358 | METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR - A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C. | 03-13-2014 |
20140159052 | METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARRIER LOWERING AND ON RESISTANCE - Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and R | 06-12-2014 |
20140183551 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 07-03-2014 |
20140197411 | METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE - A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess. | 07-17-2014 |
20140367787 | METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES - A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors. | 12-18-2014 |
20150053981 | METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE - A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess. | 02-26-2015 |
20150249129 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 09-03-2015 |
20160035630 | METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES - One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region. | 02-04-2016 |
Patent application number | Description | Published |
20150279959 | METHODS OF REMOVING PORTIONS OF FINS BY PREFORMING A SELECTIVELY ETCHABLE MATERIAL IN THE SUBSTRATE - One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate. | 10-01-2015 |
20150318169 | METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FINS OF A FINFET SEMICONDUCTOR DEVICE - One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH | 11-05-2015 |
20150318176 | FORMING ALTERNATIVE MATERIAL FINS WITH REDUCED DEFECT DENSITY BY PERFORMING AN IMPLANTATION/ANNEAL DEFECT GENERATION PROCESS - One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material. | 11-05-2015 |
20150372084 | RAISED FIN STRUCTURES AND METHODS OF FABRICATION - A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench. | 12-24-2015 |
Patent application number | Description | Published |
20140088313 | SUBSTITUTED INDOLOCARBAZOLES - A substituted indolocarbazole comprising at least one optionally substituted thienyl. | 03-27-2014 |
20150070454 | THERMALLY CONDUCTIVE AQUEOUS TRANSFIX BLANKET - An intermediate transfer member containing a thermally conductive nanofiller dispersed in a polymer base, a method of forming the intermediate transfer member, and a method of printing an image to a substrate using the intermediate transfer member. | 03-12-2015 |
20150086805 | METHOD FOR FORMING METAL STRUCTURES - A method of forming a metal structure. The method comprises providing a dispersion of metal nanoparticles and a solution comprising a transient polymer and solvent. The dispersion of metal nanoparticles and the solution are formed by coaxially electrospinning into a fiber comprising the metal nanoparticles and the transient polymer. The fiber is heated to decompose the transient polymer and form a metallic structure. | 03-26-2015 |
20150093169 | GRAPHENE AND FLUORPOLYMER COMPOSITE FUSER COATING - A fuser comprises a substrate and a composite layer formed on the substrate. The composite layer comprises a plurality of fluorosilane-treated graphene-comprising particles and a fluoropolymer. Methods of making a fuser and methods of fusing toner particles are also disclosed. | 04-02-2015 |
20150140319 | FUSER MEMBER AND METHOD OF MANUFACTURE - A fuser member including a substrate and a release layer disposed on the substrate is provided. The fuser member includes a substrate and a release layer disposed on the substrate. The release layer includes non-woven polymer fibers having graphene particles dispersed along the fibers. A method of manufacturing the release layer is provided. | 05-21-2015 |
20150140320 | SURFACE LAYER AND FUSER MEMBER - Described is a fuser member including a substrate and a release layer disposed on the substrate. The release layer includes a fluoropolymer having a plurality of metal fibers having a diameter of from about 5 nanometers to about 20 microns dispersed throughout the fluoropolymer. A method of manufacturing the fuser member is also provided. | 05-21-2015 |
20150140881 | FUSER MEMBER AND COMPOSITION OF MATTER - Described is provided a composition of matter that includes a layer having a metal coated non-woven polymer fiber mesh. The metal coated non-woven polymer fiber mesh has pores of a size of from about 1 micron to about 50 microns, and a fluoropolymer dispersed on and throughout the metal coated non-woven polymer fiber mesh. A method of manufacturing is also provided. | 05-21-2015 |
20150140882 | FUSER MEMBER AND METHOD OF MANUFACTURE - A fuser member including a substrate and a release layer disposed on the substrate is described. The release layer includes a metal coated non-woven polymer fiber mesh wherein the metal coated non-woven polymer fiber mesh has pores of a size of from about 1 microns to about 50 microns and a fluoropolymer dispersed on and throughout the polymer matrix. A method of manufacturing the fuser member is also provided. | 05-21-2015 |
20150273817 | AQUEOUS INK JET BLANKET - There is described a transfer member or blanket for use in aqueous ink jet printer. The transfer member includes a non-woven polymer fiber matrix and a polymer dispersed throughout the non-woven polymer fiber matrix. The polymer fiber matrix has a first surface energy and the polymer has a second surface energy. The difference between the first surface energy and the second surface energy is from about 30 mJ/m | 10-01-2015 |
20150321467 | AQUEOUS INK JET BLANKET - There is described a transfer member or blanket for use in aqueous ink jet printer. The transfer member includes a surface layer having a surface roughness (Ra) of from about 50 nm to about 5 microns. The surface layer has a surface energy between 8 mN/m | 11-12-2015 |
20160089876 | AQUEOUS INK JET BLANKET - There is described a transfer member or blanket for use in aqueous ink jet printer. The transfer member includes a non-woven polymer fiber matrix and a polymer dispersed throughout the non-woven polymer fiber matrix. The polymer fiber matrix has a first surface energy and the polymer has a second surface energy. The difference between the first surface energy and the second surface energy is from about 30 mJ/m | 03-31-2016 |
Patent application number | Description | Published |
20100124676 | MANAGING GAS BUBBLES IN A LIQUID FLOW SYSTEM - A system and method for managing gas bubbles in a liquid flow system are described. In particular, according to the system and method, novel techniques reduce a volume of cavities in the liquid flow system and limit a cross-sectional area of the liquid flow system to a maximum cross-sectional area of tolerably sized bubbles. In this manner, by reducing the cavity volumes and limiting cross-sectional areas, the formation of intolerably sized bubbles and the aggregation of tolerably sized bubbles into intolerably sized bubbles are each substantially prevented. Also, bubbles may be removed from the system to reduce the quantity of bubbles that are to be managed. | 05-20-2010 |
20100124678 | FUEL CELL FEED SYSTEMS - Fuel feed systems capable of providing substantially consistent flow of fuel to a fuel cell and also capable of tolerating varying pressures from a reservoir (also referred to as fuel supply or fuel cell cartridge) and the fuel cell while maintaining substantially consistent control flow to the fuel cell are disclosed. | 05-20-2010 |
20100124679 | METHOD FOR INCREASING THE DURABILITY OF DIRECT OXIDATION FUEL CELLS - Methods for increasing the durability of direct oxidation fuel cells are disclosed. In one instance, the method for increasing durability of a vapor fed direct oxidation fuel cell includes reducing fluctuations in output power, provided by the vapor fed direct oxidation fuel cell, to a load. The reduction of the fluctuations in output power can include, in one instance, utilizing a mass flow controller or an electro-osmotive pump to supply fuel to the vapor fed direct oxidation fuel cell. | 05-20-2010 |
20100124689 | SYSTEM TO RESERVOIR CONNECTOR - A system-to-reservoir connector is disclosed in which a system-side-sub-connector and a reservoir-side-sub-connector provide for a fluid connection that is resilient to external forces, is substantially leak-proof upon insertion and retraction, and is orientation independent. | 05-20-2010 |
20140127610 | FUEL CELL FEED SYSTEMS - Fuel feed systems capable of providing substantially consistent flow of fuel to a fuel cell and also capable of tolerating varying pressures from a reservoir (also referred to as fuel supply or fuel cell cartridge) and the fuel cell while maintaining substantially consistent control flow to the fuel cell are disclosed. | 05-08-2014 |