Patent application number | Description | Published |
20130145107 | IDLE POWER CONTROL IN MULTI-DISPLAY SYSTEMS - A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency. | 06-06-2013 |
20130155081 | POWER MANAGEMENT IN MULTIPLE PROCESSOR SYSTEM - Power management for a processing system that has multiple processing units, (e.g., multiple graphics processing units (GPUs), is described herein. The processing system includes a power manager that obtains performance, power, operational or environmental data from a power management unit associated with each processor (e.g., GPU). The power manager determines, for example, an average value with respect to at least one of the performance, power, operational or environmental data. If the average value is below a predetermined threshold for a predetermined amount of time, then the power manager notifies a configuration manager to alter the number of active processors (e.g., GPUs), if possible. The power may then be distributed among the remaining GPUs or other processors, if beneficial for the operating and environmental conditions. | 06-20-2013 |
20130166885 | METHOD AND APPARATUS FOR ON-CHIP TEMPERATURE - When an instruction is executed on an integrated circuit (IC), an activity level and temperature are measured. A relationship between the activity level and temperature is determined, to estimate the temperature from the activity level. The activity level is monitored and is input to a scheduler, which estimates the IC temperature based on the activity level. The scheduler distributes work taking into account the temperature of various IC regions and may include distributing work to the IC region that has a lowest estimated temperature or relatively lower estimated temperature (e.g., lower than the average IC or IC region temperature). When the utilization level of one or more IC regions is high, the scheduler is configured to reduce the clock speed or the voltage of the one or more IC regions, or flag the regions as being unavailable for additional workload. | 06-27-2013 |
Patent application number | Description | Published |
20130124900 | PROCESSOR WITH POWER CONTROL VIA INSTRUCTION ISSUANCE - Methods and apparatuses are provided for power control in a processor. The apparatus comprises a plurality of operational units arranged as a group of operational units. A power consumption monitor determines when cumulative power consumption of the group of operational units exceeds a threshold (e.g., either or both of the cumulative power threshold and the cumulative power rate threshold) during a time interval, after which a filter for issuing instructions to the group of operational units suspends instruction issuance to the group of operational units for the remainder of the time interval. The method comprises monitoring cumulative power consumption by a group of operational units within a processor over a time interval. If the cumulative power consumption of the group of operational units exceeds the threshold, instruction issuance to the group of operational units is suspended for the remainder of the time interval. | 05-16-2013 |
20130138977 | METHOD AND APPARATUS FOR ADJUSTING POWER CONSUMPTION LEVEL OF AN INTEGRATED CIRCUIT - Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency. | 05-30-2013 |
20130155045 | METHOD AND APPARATUS FOR POWER MANAGEMENT OF A GRAPHICS PROCESSING CORE IN A VIRTUAL ENVIRONMENT - A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request. | 06-20-2013 |
20130155073 | METHOD AND APPARATUS FOR POWER MANAGEMENT OF A PROCESSOR IN A VIRTUAL ENVIRONMENT - A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core. | 06-20-2013 |
20130159755 | APPARATUS AND METHOD FOR MANAGING POWER ON A SHARED THERMAL PLATFORM FOR A MULTI-PROCESSOR SYSTEM - A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform. | 06-20-2013 |