Patent application number | Description | Published |
20120330616 | FREQUENCY GUARD BAND VALIDATION OF PROCESSORS - A frequency guard band validation unit can determine whether at least one of a plurality of previously validated processors was validated on a first system having a substantially similar configuration as a second system in which an unvalidated processor is being tested. If at least one of the plurality of previously validated processors was validated on the first system, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency. This can reduce the overall validation cycle time. | 12-27-2012 |
20130103354 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 04-25-2013 |
20130103927 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 04-25-2013 |
20140053016 | Using A Buffer To Replace Failed Memory Cells In A Memory Component - Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component. | 02-20-2014 |
20140059327 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 02-27-2014 |
20140082335 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 03-20-2014 |
20140112754 | Thermal Control System Based on Nonlinear Zonal Fan Operation and Optimized Fan Power - An approach is provided in which a cooling manager retrieves pre-characterization data corresponding to a fan that electronic components included in a computer system. The pre-characterization data includes operational zones based upon fan power measurements and fan speed settings. The cooling manager sets the fan to a first speed setting within a first operational zone, and detects that one of the components generates a temperature change value that exceeds a specified temperature change value corresponding to the component. In turn, the cooling manager selects a second operational zone and sets the fan to a second speed setting within the second operational zone. | 04-24-2014 |
20140114496 | Thermal Control System Based on Nonlinear Zonal Fan Operation and Optimized Fan Power - An approach is provided in which a cooling manager retrieves pre-characterization data corresponding to a fan that electronic components included in a computer system. The pre-characterization data includes operational zones based upon fan power measurements and fan speed settings. The cooling manager sets the fan to a first speed setting within a first operational zone, and detects that one of the components generates a temperature change value that exceeds a specified temperature change value corresponding to the component. In turn, the cooling manager selects a second operational zone and sets the fan to a second speed setting within the second operational zone. | 04-24-2014 |
20140157044 | IMPLEMENTING DRAM FAILURE SCENARIOS MITIGATION BY USING BUFFER TECHNIQUES DELAYING USAGE OF RAS FEATURES IN COMPUTER SYSTEMS - A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data. | 06-05-2014 |
20140359241 | MEMORY DATA MANAGEMENT - A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found. | 12-04-2014 |
20140359310 | SUBSYSTEM-LEVEL POWER MANAGEMENT IN A MULTI-NODE VIRTUAL MACHINE ENVIRONMENT - A computer-implemented method includes capping the amount of power available to each of a plurality of compute nodes, and managing power allocation among subsystems within each of the compute nodes according to the requirements of workloads assigned to each of the compute nodes. The method further comprises reporting an actual performance level and performance capability for each subsystem within each of the plurality of compute nodes, and monitoring parametric data for a particular workload. A target compute node is identified from among the compute nodes, wherein the target compute node would be capable of performing the particular workload if power was reallocated from a first subsystem to a second subsystem within the target compute node. The particular workload is then assigned to the target compute node. Optionally, assigning the particular workload may include migrating the workload to the target compute node from another of the compute nodes. | 12-04-2014 |
20140379288 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 12-25-2014 |
20150057975 | FREQUENCY GUARD BAND VALIDATION OF PROCESSORS - It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency. | 02-26-2015 |