Powerchip Technology Corporation
Powerchip Technology Corporation, Hsinchu TW
Patent application number | Description | Published |
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20130130471 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 05-23-2013 |
20130203228 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed. | 08-08-2013 |
Powerchip Technology Corporation, Hsin-Chu TW
Patent application number | Description | Published |
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20130200328 | PHASE CHANGE MEMORY DEVICES - A phase change memory device is provided, including: a substrate; a first dielectric layer disposed over the substrate; a first electrode disposed in the first dielectric layer; a second dielectric layer formed over the first dielectric layer, covering the first electrode; a heating electrode disposed in the second dielectric layer, contacting the first electrode; a phase change material layer disposed over the second dielectric layer, contacting the heating electrode; and a second electrode disposed over the phase change material layer, wherein the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides, and the first portion of the heating electrode includes no metal silicides, and includes refractory metal materials or noble metal materials. | 08-08-2013 |
Powerchip Technology Corporation US
Patent application number | Description | Published |
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20130217218 | FABRICATING METHOD OF NON-VOLATILE MEMORY - A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction. | 08-22-2013 |