Patent application number | Description | Published |
20130181905 | APPARATUS AND METHOD FOR MANAGING INSTANT MESSAGING - An electronic device includes a touch screen, a virtual keyboard projector, and a content projector. When a first touch gesture is detected by the touch screen, the virtual keyboard projector produces a projected virtual keyboard. An input content is obtained through the projected virtual keyboard and transmitted to a remote electronic device through a communication interface. The electronic device receives a messaging content from the remote electronic device. When a second touch gesture is detected by the touch screen, the content projector projects a projected display and presents the messaging content in the projected display. A method of managing instant messaging in the electronic device is also provided. | 07-18-2013 |
20140078653 | ENCLOSURE OF ELECTRONIC DEVICE WITH CUSHION PAD - An enclosure of an electronic device includes a case and a cushion pad. The case includes a bottom plate defining a receiving slot and a cutout in communication with the receiving slot. The cushion pad includes a clasp block including a connecting portion and an engaging portion. The connecting portion is received in the receiving slot and the engaging portion is inserted through the cutout. The connecting portion slides in the receiving slot to misalign the engaging portion to the cutout and have the engaging portion engaging on the bottom plate. | 03-20-2014 |
20140085785 | ELECTRONIC DEVICE WITH RUBBER PADS - An electronic device comprises a chassis and a plurality of rubber pads mounted in a base panel of the chassis. A mounting hole is defined in the base panel. A protruding wall extends from an edge of the mounting hole towards an inner side of the base panel. A groove is defined in the protruding wall. Each of the plurality of rubber pads comprises a supporting wall and a mounting portion extending from an inner side of the supporting member. The mounting portion comprises a main body mounted in the mounting hole and a latch portion extending from the main body and extending through the groove for preventing the main body from disengaging from the mounting hole. | 03-27-2014 |
20140223387 | TOUCH-SENSITIVE DEVICE AND ON-SCREEN CONTENT MANIPULATION METHOD - An electronic device includes a front panel and a side panel. A display is disposed at the front panel and configured to present content to a user. A touch-sensitive bar is disposed at the side panel and configured to receive a touch gesture input by the user. A control module is configured to manipulate the presented content according to the touch gesture. An on-screen content manipulation method is also provided. | 08-07-2014 |
Patent application number | Description | Published |
20090037786 | Method and apparatus for unifying self-test with scan-test during prototype debug and production test - A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. | 02-05-2009 |
20090132880 | Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test - A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus. | 05-21-2009 |
20130268818 | Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 10-10-2013 |
20140075256 | Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 03-13-2014 |
20140075257 | Computer-Aided Design (CAD) Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 03-13-2014 |
20140082446 | Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 03-20-2014 |
20140223251 | Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Scan-Test - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 08-07-2014 |
20140242367 | BARRIER FILM AND METHODS OF MAKING SAME - A barrier film for blocking moisture and oxygen transmission includes a single layer grown from a precursor of organic silicide by a chemical vapor deposition, having at least silicon (Si) atoms, oxygen (O) atoms and carbon (C) atoms with atomic ratios of C/Si in a range of about 0.1-0.5, and O/Si in a range of about 2.0-2.5. The Si and O atoms form four bonding structures: Si(—O)4, Si(—O)3, Si(—O)2, and Si(—O)1, in the single layer. In the total amount of the four bonding structures being 100%, the bonding structures of Si(—O)4, Si(—O)3, Si(—O)2, and Si(—O)1 are in ranges of about 50%-99.9%, 0.01%-50%, 0%-10%, and 0%-10%, respectively. | 08-28-2014 |