Plumton
Donald Plumton, Dallas, TX US
Patent application number | Description | Published |
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20090273100 | INTEGRATED CIRCUIT HAVING INTERLEAVED GRIDDED FEATURES, MASK SET AND METHOD FOR PRINTING | 11-05-2009 |
20120220133 | Integrated Circuit Having Interleaved Gridded Features, Mask Set, and Method for Printing - A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer. | 08-30-2012 |
Donald L. Plumton, Dallas, TX US
Patent application number | Description | Published |
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20130329508 | Methods And Devices For Determining Logical To Physical Mapping On An Integrated Circuit - Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern. | 12-12-2013 |
James Osborne Plumton, Enosburg, VT US
Patent application number | Description | Published |
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20120034332 | HOT-RUNNER SYSTEM HAVING BLADDER ASSEMBLY - A hot-runner system ( | 02-09-2012 |