Patent application number | Description | Published |
20100225519 | EDC ARCHITECTURE - A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply. | 09-09-2010 |
20110063151 | Systems, Circuits, and Methods for Pipelined Folding and Interpolating ADC Architecture - A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply. | 03-17-2011 |
20140022101 | TIME INTERLEAVED ANALOG TO DIGITAL CONVERTER MISMATCH CORRECTION - A machine-implemented method can include receiving a common input signal over M parallel time-interleaved (TI) analog to digital converter (ADC) channels, determining a multiple-input, multiple-output finite impulse response (FIR) filter structure for correcting bandwidth mismatches between the M parallel TIADC channels, and providing a common output signal comprising TI data corresponding to the M parallel TIADC corrected channels. | 01-23-2014 |
Patent application number | Description | Published |
20100057530 | System and Method for Electronic Transactions and Providing Consumer Rewards - A system and method for electronic transactions involves a website that displays an advertisement of a merchant. The website includes a feature that allows a visitor to the website to commit to making a purchase from the merchant within a certain period of time. The website visitor is encouraged to make the purchase by a commitment made by the merchant to donate or giveback a portion of the purchase value. When the website visitor actually makes a purchase from the merchant at a later time, the system and method allows for identification of the visitor as somebody who earlier made a purchase commitment, thereby allowing the merchant to determine whether to make a donation and to determine the effectiveness of the advertisement. | 03-04-2010 |
20110248398 | WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO MITIGATE FAILURES DUE TO STRESS - Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays. | 10-13-2011 |
20110300668 | USE OF DEVICE ASSEMBLY FOR A GENERALIZATION OF THREE-DIMENSIONAL METAL INTERCONNECT TECHNOLOGIES - An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks. | 12-08-2011 |
20120280107 | OPTICAL GESTURE SENSOR USING A SINGLE ILLUMINATION SOURCE - A gesture sensing device includes a single light source and a multiple segmented single photo sensor, or an array of photo sensors, collectively referred to herein as segmented photo sensors. A light modifying structure relays reflected light from the light source onto different segments of the segmented photo sensors. The light modifying structure can be an optical lens structure or a mechanical structure. The different segments of the photo sensor sense reflected light and output corresponding sensed voltage signals. A control circuit receives and processes the sensed voltage signals to determine target motion relative to the segmented photo sensor. | 11-08-2012 |
20120280904 | METHOD FOR DETECTING GESTURES USING A MULTI-SEGMENT PHOTODIODE AND ONE OR FEWER ILLUMINATION SOURCES - A gesture sensing device includes a multiple segmented photo sensor and a control circuit for processing sensed voltages output from the sensor. The control circuit processes the sensed voltage signals to determine target motion relative to the segmented photo sensor. The control circuit includes an algorithm configured to calculate one of more differential analog signals using the sensed voltage signals output from the segmented photo sensors. A vector is determined according to the calculated differential analog signals, the vector is used to determine a direction and/or velocity of the target motion. | 11-08-2012 |
20130173840 | COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 07-04-2013 |
20140035812 | GESTURE SENSING DEVICE - A gesture sensing device having a single illumination source is disclosed. In one or more implementations, the gesture sensing device includes a single illumination source configured to emit light and a light sensor assembly configured to detect the light reflected from an object and to output time dependent signals in response thereto. The gesture sensing device also includes a processing circuit coupled to the light sensor assembly and configured to analyze the time dependent signals received from the light sensor assembly to determine object directional movement proximate to the light sensor assembly. | 02-06-2014 |
20140095564 | System and Method with Specific Ordered Execution Over Physical Elements - The invention relates to semiconductor devices, and more particularly, to systems, devices and methods of utilizing inherent differences among physical elements in an electrical component to generate unique and non-duplicable numbers that are statistically random and repeatable. These bits may be applied as identifications, random number seeds or encryption keys in many security applications, e.g., a financial terminal. An integrator is coupled to a plurality of physical elements, selects two physical elements or element sets, and generates an integrated difference signal according to a difference between these two physical elements or element sets. A comparison-decision logic further determines whether the difference between the selected two physical elements is associated with a bit of “1” or “0”. In some embodiments, a multi-bit number constitutes multiple bits each of which may be derived from a difference between two randomly selected physical elements or element sets. | 04-03-2014 |
20140183747 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 07-03-2014 |
20140252655 | FAN-OUT AND HETEROGENEOUS PACKAGING OF ELECTRONIC COMPONENTS - Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate. | 09-11-2014 |
20140264711 | LIGHT SENSOR WITH VERTICAL DIODE JUNCTIONS - Light sensors are described that include a trench structure integrated therein. In an implementation, the light sensor includes a substrate having a dopant material of a first conductivity type and multiple trenches disposed therein. The light sensor also includes a diffusion region formed proximate to the multiple trenches. The diffusion region includes a dopant material of a second conductivity type. A depletion region is created at the interface of the dopant material of the first conductivity type and the dopant material of the second conductivity type. The depletion region is configured to attract charge carriers to the depletion region, at least substantially a majority of the charge carriers generated due to light incident upon the substrate. | 09-18-2014 |
20140284462 | OPTICAL GESTURE SENSOR HAVING A LIGHT MODIFYING STRUCTURE - A gesture sensing device includes a single light source and a multiple segmented single photo sensor, or an array of photo sensors, collectively referred to herein as segmented photo sensors. A light modifying structure relays reflected light from the light source onto different segments of the segmented photo sensors. The light modifying structure can be an optical lens structure or a mechanical structure. The different segments of the photo sensor sense reflected light and output corresponding sensed voltage signals. A control circuit receives and processes the sensed voltage signals to determine target motion relative to the segmented photo sensor. | 09-25-2014 |
20150019790 | COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE - A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch. | 01-15-2015 |
20150325512 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 11-12-2015 |