Patent application number | Description | Published |
20100174819 | METHOD FOR PROCESSING REGISTER REQUEST, NETWORK ELEMENT, AND COMMUNICATION SYSTEM - The invention provides a method for processing register request, network element, and a communication system. The method for processing a register request of a terminal in a communication system that comprises a first network element (GSN) for providing IP networking service to said terminal, a second network element (P-CSCF) for providing SIP proxy service to said terminal, a third network element (S-CSCF) for providing SIP subscriber service to said terminal, and a fourth network element (HSS) for storing information about said terminal including said terminal's address; wherein the communication system further comprises a fifth network element (NAPT) for translating said terminal's address in between said first network element and said second network element; said method comprise: determining whether a message issued by said terminal for said register request has undergone Network Address Port Translation; indicating an address for address verification in said message based on the determination whether said message has undergone Network Address Port Translation; and verifying the address for address verification in said message against the information stored in said fourth network element. | 07-08-2010 |
20100327314 | Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method - This invention discloses an IGBT device with its collector formed with Ge/Al and associated method of fabrication. The collector is formed on the substrate layer, which is on the back of IGBT, and contains Ge and Al thin films. After thinning and etching the back side of IGBT substrate, Ge and Al are sequentially deposited to form Ge/Al thin films on the back surface of the substrate. An annealing process is then carried out to diffuse Al into Ge thin film layer to form a P-doped Ge layer functioning as the IGBT collector. The present invention is applicable to both non punch through IGBTs as well as punch through IGBTs. | 12-30-2010 |
20110016314 | METHODS AND ENTITIES USING IPSec ESP TO SUPPORT SECURITY FUNCTIONALITY FOR UDP-BASED OMA ENABLES - Methods in OMA SEC_CF for providing security services to traffic over UDP between a client and a server and the relevant entities are provided. A pre-shared key is pre-shared between the client and the server. A pair of IPSec ESP SAs between the client and the server is established without shared key negotiation, wherein traffic data cryptographic algorithms are determined. Traffic data security keys are derived from the pre-shared key via the determined traffic data cryptographic algorithms. Then, data of the traffic can be provided with security services with the traffic data security keys through use of IPSec ESP. | 01-20-2011 |
20110294262 | SEMICONDUCTOR PACKAGE PROCESS WITH IMPROVED DIE ATTACH METHOD FOR ULTRATHIN CHIPS - A semiconductor packaging process with improved die attach method for ultrathin chips package comprises the steps of providing a semiconductor wafer having a wafer frontside and a wafer backside with a plurality of integrated circuit chips (IC chips) formed on the wafer frontside; adhering a supporting substrate onto the wafer frontside through a bonding layer to form a wafer combo; grinding the wafer backside with the supporting substrate and the wafer bonded together; dicing the wafer combo into a plurality of die combos each comprising a substrate piece stacked on top of an IC chip bonded by a bonding layer piece; attaching a die combo onto a die pad of a lead frame with a bottom of the IC chip connected to the lead frame thereof; and removing the substrate piece with the bonding layer piece from the top surface of the IC chip. | 12-01-2011 |
20120104580 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed. | 05-03-2012 |
20120142165 | Method of Avoiding Resin Outflow from the Wafer Scribe line in WLCSP - A preparation process of wafer level chip scale packaging that prevents damaging a wafer in molding process is disclosed. In this process, a grinding grove is formed at a top side and around the edge of a wafer before molding is performed. The grinding groove effectively prevents the molding material from overflowing to the edge of the wafer, which avoids the damage of the wafer. | 06-07-2012 |
20140242756 | METHOD FOR PREPARING SEMICONDUCTOR DEVICES APPLIED IN FLIP CHIP TECHNOLOGY - A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices. | 08-28-2014 |
20140264805 | Semiconductor Package And Fabrication Method Thereof - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 09-18-2014 |
20140319601 | BOTTOM SOURCE SUBSTRATELESS POWER MOSFET - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 10-30-2014 |
20150021753 | PACKAGING STRUCTURE OF A SEMICONDUCTOR DEVICE - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 01-22-2015 |
20150021780 | THIN POWER DEVICE AND PREPARATION METHOD THEREOF - A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads. | 01-22-2015 |
20150031644 | AMPHIPHILIC DRUG-DRUG CONJUGATES FOR CANCER THERAPY, COMPOSITIONS AND METHODS OF PREPARATION AND USES THEREOF - The invention provides novel amphiphilic drug-drug conjugates useful as cancer therapeutics, and compositions and methods thereof. | 01-29-2015 |
20150056752 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer. | 02-26-2015 |
20150087114 | METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE - A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process. | 03-26-2015 |
Patent application number | Description | Published |
20080245892 | Decay prevention structure of a heat dissipating board of a humidifier - A humidifier includes a water storage tank for storing water, a working tank, a piezoelectric crystal, a filtering unit, and a heat dissipating board; the filtering unit is positioned in the storage tank for filtering water before water is sent from the water storage tank into the working tank; the piezoelectric crystal will vibrate so as to produce ultrasonic waves to break water contained in the working tank into molecules, which will dissolve in air immediately; the heat dissipating board is interposed between an upper side of the piezoelectric crystal and water contained in the working tank so as to be in touch with the water; the heat dissipating board has a decay-prevention stainless steel layer joined to an upper side thereof therefore it is prevented from decaying and rusting. | 10-09-2008 |
20090277785 | Coaxial symmetrical completely open electrolytic bath - An electrolytic bath includes a shell, an upper cover joined on an upper end of the shell, an outer supporting member held in the shell, a hollow cylindrical positive electrode plate held in the outer supporting member, a hollow cylindrical negative electrode plate held in the positive electrode plate, an inner supporting member held in the negative electrode plate, a lower cover joined on a lower end of the shell, and a base member on a bottom of the lower cover; a space exists between the positive and the negative electrode plates; the electrolytic bath has a waste water outlet and a water outlet hole for acid waste water and alkaline water to flow out therethrough respectively; because the electrode plates are hollow cylindrical and completely open, they can't change shape easily, and there is no need for a separating plate, and scale can't form on the electrode plates easily. | 11-12-2009 |
Patent application number | Description | Published |
20120032259 | BOTTOM SOURCE POWER MOSFET WITH SUBSTRATELESS AND MANUFACTURING METHOD THEREOF - A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface. | 02-09-2012 |
20120235289 | POWER DEVICE WITH BOTTOM SOURCE ELECTRODE AND PREPARATION METHOD - A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process. | 09-20-2012 |
20130037935 | WAFER LEVEL PACKAGE STRUCTURE AND THE FABRICATION METHOD THEREOF - The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections. | 02-14-2013 |
20130095612 | WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP - A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip. | 04-18-2013 |
20130130443 | METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRESSION IN WAFER LEVEL PACKAGING PROCESS - The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip. | 05-23-2013 |
20130210195 | PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) - A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove. | 08-15-2013 |
20130210215 | PACKAGING METHOD WITH BACKSIDE WAFER DICING - A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside. | 08-15-2013 |
Patent application number | Description | Published |
20120079773 | METHOD OF FABRICATING A POLISHING PAD WITH AN END-POINT DETECTION REGION FOR EDDY CURRENT END-POINT DETECTION - Methods of fabricating polishing pads with end-point detection regions for polishing semiconductor substrates using eddy current end-point detection are described. | 04-05-2012 |
20120083191 | POLISHING PAD FOR EDDY CURRENT END-POINT DETECTION - Polishing pads for polishing semiconductor substrates using eddy current end-point detection are described. Methods of fabricating polishing pads for polishing semiconductor substrates using eddy current end-point detection are also described. | 04-05-2012 |
20120083192 | HOMOGENEOUS POLISHING PAD FOR EDDY CURRENT END-POINT DETECTION - Homogeneous polishing pads for polishing semiconductor substrates using eddy current end-point detection are described. Methods of fabricating homogeneous polishing pads for polishing semiconductor substrates using eddy current end-point detection are also described. | 04-05-2012 |
20120094586 | POLISHING PAD WITH MULTI-MODAL DISTRIBUTION OF PORE DIAMETERS - Polishing pads with multi-modal distributions of pore diameters are described. Methods of fabricating polishing pads with multi-modal distributions of pore diameters are also described. | 04-19-2012 |
20120302148 | POLISHING PAD WITH HOMOGENEOUS BODY HAVING DISCRETE PROTRUSIONS THEREON - Polishing pads with homogeneous bodies having discrete protrusions thereon are described. In an example, a polishing pad for polishing a substrate includes a homogeneous body having a polishing side and a back side. The homogeneous body is composed of a material having a first hardness. A plurality of discrete protrusions is disposed on and covalently bonded with the polishing side of the homogeneous body. The plurality of discrete protrusions is composed of a material having a second hardness different from the first hardness. Methods of fabricating polishing pads with homogeneous bodies having discrete protrusions thereon are also described. | 11-29-2012 |
20140167305 | POLISHING PAD WITH MULTI-MODAL DISTRIBUTION OF PORE DIAMETERS - Polishing pads with multi-modal distributions of pore diameters are described. Methods of fabricating polishing pads with multi-modal distributions of pore diameters are also described. | 06-19-2014 |
20150056900 | POLISHING PAD WITH HOMOGENEOUS BODY HAVING DISCRETE PROTRUSIONS THEREON - Polishing pads with homogeneous bodies having discrete protrusions thereon are described. In an example, a polishing pad for polishing a substrate includes a homogeneous body having a polishing side and a back side. The homogeneous body is composed of a material having a first hardness. A plurality of discrete protrusions is disposed on and covalently bonded with the polishing side of the homogeneous body. The plurality of discrete protrusions is composed of a material having a second hardness different from the first hardness. Methods of fabricating polishing pads with homogeneous bodies having discrete protrusions thereon are also described. | 02-26-2015 |
Patent application number | Description | Published |
20130206009 | VERTICAL TYPE AIR HUMIDIFYING AND PURIFYING MACHINE - A vertical type air humidifying and purifying machine, comprising a front casing, a rear casing, a humidifying unit, an ultraviolet light purifying unit, a motor-fan unit and a negative ion generator; in which the front casing and the rear casing are assembled correspondingly with each other, and the humidifying unit, the UV light purifying unit, and the motor-fan unit are disposed orderly between the front and the rear casings, and the negative ion generator is installed at an air outlet of the motor-fan unit; ON-OFF switches being respectively provided on the humidifying unit, the UV purifying unit and the negative ion generator for ON-OFF switching. | 08-15-2013 |
20140123694 | COOLING FAN WITH ATOMIZING DEVICE - A cooling fan includes a body and a motor is connected to the body, the motor drives multiple blades. An atomizing device is connected to the body and has an oscillator beside which a blowing device is located. A guide pipe has the first end thereof connected to the oscillator and the second end of the guide pipe extends beyond the blades. A water tank is connected to the body and has a valve which is located corresponding to the oscillator. By the rotation of the blades, the atomized water particles are sent to cool the heat. | 05-08-2014 |
Patent application number | Description | Published |
20130324020 | POLISHING PAD WITH POLISHING SURFACE LAYER HAVING AN APERTURE OR OPENING ABOVE A TRANSPARENT FOUNDATION LAYER - Polishing pads with a polishing surface layer having an aperture or opening above a transparent foundation layer are described. In an example, a polishing pad for polishing a substrate includes a foundation layer having a global top surface and a transparent region. A polishing surface layer is attached to the global top surface of the foundation layer. The polishing surface layer has a polishing surface and a back surface. An aperture is disposed in the polishing pad from the back surface through to the polishing surface of the polishing surface layer, and aligned with the transparent region of the foundation layer. The foundation layer provides an impermeable seal for the aperture at the back surface of the polishing surface layer. Methods of fabricating such polishing pads are also described. | 12-05-2013 |
20140102010 | Polishing Pad for Eddy Current End-Point Detection - Polishing pads for polishing semiconductor substrates using eddy current end-point detection are described. Methods of fabricating polishing pads for polishing semiconductor substrates using eddy current end-point detection are also described. | 04-17-2014 |
20140123563 | HOMOGENEOUS POLISHING PAD FOR EDDY CURRENT END-POINT DETECTION - Homogeneous polishing pads for polishing semiconductor substrates using eddy current end-point detection are described. Methods of fabricating homogeneous polishing pads for polishing semiconductor substrates using eddy current end-point detection are also described. | 05-08-2014 |
20140206268 | POLISHING PAD HAVING POLISHING SURFACE WITH CONTINUOUS PROTRUSIONS - Polishing pads having a polishing surface with continuous protrusions are described. Methods of fabricating polishing pads having a polishing surface with continuous protrusions are also described. | 07-24-2014 |
20140273777 | POLISHING PAD HAVING POLISHING SURFACE WITH CONTINUOUS PROTRUSIONS HAVING TAPERED SIDEWALLS - Polishing pads having a polishing surface with continuous protrusions having tapered sidewalls are described. Methods of fabricating polishing pads having a polishing surface with continuous protrusions having tapered sidewalls are also described. | 09-18-2014 |
20150038066 | LOW DENSITY POLISHING PAD - Low density polishing pads and methods of fabricating low density polishing pads are described. In an example, a polishing pad for polishing a substrate includes a polishing body having a density of less than 0.5 g/cc and composed of a thermoset polyurethane material. A plurality of closed cell pores is dispersed in the thermoset polyurethane material. | 02-05-2015 |