| Patent application number | Description | Published |
|---|
| 20080232185 | Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures - A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 09-25-2008 |
| 20080276214 | METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE - Connection assignments of differential signals within an integrated circuit (IC) package are automatically made in the design and manufacturing process of the IC package, for use in automated computing systems. Either predefined pairs of pins at both ends or pairs of pins automatically paired or a combination of both are used in the creation of an imaginary pin or midpoint between the pair. Then the point-to-point connections of the pair are automatically detangled. Once the imaginary midpoint-to-midpoint connections are created, the real differential connections can then be assigned. | 11-06-2008 |
| 20090031067 | Spider Web Interconnect Topology Utilizing Multiple Port Connection - A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke. | 01-29-2009 |
| 20090055134 | System and Method for Implementing Optimized Creation of Openings for De-Gassing in an Electronic Package - System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. The placement manager inserts specifications for at least one de-gassing opening in the physical design for the electronic package, wherein the specification for at least one de-gassing opening are created in accordance with said design constraints regarding said physical design of said electronic package. The placement manager outputs an updated physical design of the electronic package. | 02-26-2009 |
| 20090056350 | BIMETALLIC HEAT SINK AIR DEFLECTORS FOR DIRECTED AIRFLOW FOR IMPROVED THERMAL TRANSFER AND DISSIPATION - A cooling apparatus, includes: one or more bimetallic deflectors attached to a mounting post, the mounting post configured for mating engagement with a protrusion of a heat sink, such that the one or more bimetallic deflectors are in thermal contact with the protrusion when the mounting post is engaged therewith; wherein the bimetallic deflectors are configured to deflect in response to thermal energy conducted from the protrusions so as to change a direction of airflow incident thereupon. | 03-05-2009 |
| 20090058425 | METHOD AND APPARATUS TO TEST ELECTRICAL CONTINUITY AND REDUCE LOADING PARASITICS ON HIGH-SPEED SIGNALS - An apparatus for testing electrical continuity of a surface mounted (SMT) electrical board includes: a printed wiring board having a first surface and an opposite second surface; a conductive signal line disposed on each of the first and second surfaces of the printed wiring board; an electrical component disposed on and electrically connected to the conductive signal line on the first surface; and a through hole extending through the printed wiring board and the conductive signal line on the second surface of the printed wiring board exposing a surface side of the conductive signal line facing the first surface of the printed wiring board. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board. | 03-05-2009 |
| 20090079060 | METHOD AND STRUCTURE FOR DISPENSING CHIP UNDERFILL THROUGH AN OPENING IN THE CHIP - A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole. | 03-26-2009 |
| 20090196118 | Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures - A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 08-06-2009 |
| 20090305463 | System and Method for Thermal Optimized Chip Stacking - A method for thermal optimization comprising the steps of stacking a first chip layer and a second chip layer wherein the second chip layer is rotated in relation to the first chip layer wherein a first hot spot on the first chip layer and a second hot spot on the second chip layer are not spatially aligned; routing a signal input through the first chip layer from a first chip pad on the first chip layer to a first silicon via so as to form a physical input to output twist and a first signal output; and routing the first signal output from the first chip layer through a second chip layer from a second chip pad on the second chip layer to a second silicon via so as to form a second signal output. | 12-10-2009 |
| 20100025479 | Doped Implant Monitoring for Microchip Tamper Detection - A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation. | 02-04-2010 |
| 20100025864 | SHIELDED WIREBOND - A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the first coating, in electrical communication with the ground pads. The first coating is sufficiently thick to achieve a consistent characteristic impedance when the second coating is applied. | 02-04-2010 |
| 20100026313 | Capacitance Structures for Defeating Microchip Tampering - Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically comprise metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip. | 02-04-2010 |
| 20100026326 | Resistance Sensing for Defeating Microchip Exploitation - A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis. | 02-04-2010 |
| 20100026336 | FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION - An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected. | 02-04-2010 |
| 20100026337 | Interdependent Microchip Functionality for Defeating Exploitation Attempts - An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects. | 02-04-2010 |
| 20100026506 | Capacitance-Based Microchip Exploitation Detection - An apparatus and method detect microchip tampering by including a capacitance circuit that comprises a protective cover. Dielectric material may be sandwiched between the cover and a backside metal layer, which may be proximate a protected surface of the microchip. Changes in the capacitance of the above circuit caused by alteration of the cover or other component of the capacitance circuit may be sensed and prompt defensive action. | 02-04-2010 |
| 20100031375 | Signal Quality Monitoring to Defeat Microchip Exploitation - Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process. | 02-04-2010 |
| 20100031376 | Continuity Check Monitoring for Microchip Exploitation Detection - Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt. | 02-04-2010 |
