Patent application number | Description | Published |
20100096672 | SELF-ALIGNED, INTEGRATED CIRCUIT CONTACT - Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits. | 04-22-2010 |
20110212618 | TRENCH INTERCONNECT STRUCTURE AND FORMATION METHOD - Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in reduced interconnect resistance, I | 09-01-2011 |
20110254163 | SLEEVE INSULATORS AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components. | 10-20-2011 |
20110278738 | SELF-ALIGNED, INTEGRATED CIRCUIT CONTACT - This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated portions of overlying conductive material due to contact misalignment. | 11-17-2011 |
20120068348 | Interconnect Regions - Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous. | 03-22-2012 |
20120267786 | MICROELECTRONIC DEVICES WITH THROUGH-SILICON VIAS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material. | 10-25-2012 |
20120306084 | Semiconductor Constructions Having Through-Substrate Interconnects, and Methods of Forming Through-Substrate Interconnects - Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect. | 12-06-2012 |
20120326283 | Interconnect Regions - Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous. | 12-27-2012 |
20130026647 | VIA STRUCTURE - A via structure includes at least a first via set and a second via set electrically connected to the first via set. There is at least one via in the first via set and at least one via in the second via set. The via in the first via set has a cross-sectional area which is larger than that of the via in the second via set. | 01-31-2013 |
20130034119 | VIA CHAIN TESTING STRUCTURE AND METHOD - A via chain testing structure includes: a substrate; a dielectric layer disposed on the substrate; a first via chain disposed on dielectric layer; a second via chain, being disposed on the dielectric on both sides of the first via chain and in thermal proximity with the first via chain; a first heating source disposed under the substrate, for providing thermal heat to the first via chain; and an electrical current source for heating the second via chain so the second via chain acts as a second heating source for the first via chain. | 02-07-2013 |
20140287584 | MICROELECTRONIC DEVICES WITH THROUGH-SILICON VIAS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material. | 09-25-2014 |