Patent application number | Description | Published |
20080269798 | EMBOLECTOMY DEVICE - An embodiment is a catheter comprising a first elongate shaft having a proximal end, a distal end and a first lumen therethrough, a wire having a proximal end and a distal end at least partially disposed in the first elongate shaft, the distal end extending distally from the first elongate shaft, and a motion control apparatus connected to the proximal end of the wire, further comprising a device attached to the distal end of the wire for changing the shape of an embolus, wherein the device is configured to change the shape of the embolus to unclog a distal catheter lumen. | 10-30-2008 |
20100222806 | EMBOLUS EXTRACTOR - An embolus extractor including elongate shaft having a proximal end and a distal end. The embolus extractor may include primary struts coupled to the distal end of the shaft. The struts may define a proximally disposed mouth. Additional secondary struts may be coupled along the elongate shaft to enhance the thrombus containing ability of the embolus extractor. | 09-02-2010 |
20110218560 | EMBOLECTOMY DEVICE - An embodiment is a catheter comprising a first elongate shaft having a proximal end, a distal end and a first lumen therethrough, a wire having a proximal end and a distal end at least partially disposed in the first elongate shaft, the distal end extending distally from the first elongate shaft, and a motion control apparatus connected to the proximal end of the wire, further comprising a device attached to the distal end of the wire for changing the shape of an embolus, wherein the device is configured to change the shape of the embolus to unclog a distal catheter lumen. | 09-08-2011 |
Patent application number | Description | Published |
20090161434 | Read, Verify Word Line Reference Voltage to Track Source Level - A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop. | 06-25-2009 |
20100073069 | On-Chip Bias Voltage Temperature Coefficient Self-Calibration Mechanism - Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor. | 03-25-2010 |
20100157681 | Read, Verify Word Line Reference Voltage to Track Source Level - A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop. | 06-24-2010 |
20110018617 | Charge Pump with Reduced Energy Consumption Through Charge Sharing and Clock Boosting Suitable for High Voltage Word Line in Flash Memories - A charge pump circuit for generating an output voltage is described. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler | 01-27-2011 |
20130076432 | HIGH VOLTAGE CHARGE PUMP REGULATION SYSTEM WITH FINE STEP ADJUSTMENT - A regulator system for a charge pump system divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine output voltage steps. The other branch controls a serial resistor to provide the large step size. For example, a 9-bit digital input signal is split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments. In the example of a 50 mV step size, in one current path 2 bits of the binary input then control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements. | 03-28-2013 |
20140375293 | Capacitive Regulation of Charge Pumps Without Refresh Operation Interruption - In a charge pump system using a capacitive voltage divider, or other feedback circuit requiring periodic refreshing, in order to refresh the circuit, system operations would typically need to be suspended in order to refresh the capacitors if charge leakage begins to affect the output level. This can lead to delay and power inefficiencies. To overcome this, two feedback circuits are used so that while one is active, the other can have its capacitors' state refreshed. By alternating the two networks, delay can be avoided and power use reduced. | 12-25-2014 |