Patent application number | Description | Published |
20130191346 | SIMULATION CONTROL TECHNIQUES - Simulation control techniques include shutting down peer processes and user code modules, storing an image of a simulation as a checkpoint after the peer processes and user code modules are shutdown, and re-starting user code modules and peer processes after storing an image of the simulation. The resulting checkpoint and processes can be used for restoring from a checkpoint or restarting a new simulation environments having peer processes such as debuggers coupled to the simulation. | 07-25-2013 |
20130212566 | COORDINATING AND CONTROLLING DEBUGGERS IN A SIMULATION ENVIRONMENT - A simulation environment, in one embodiment, includes a debugger server, one or more debuggers, and one or more debugger adapters. Each debugger adapter couples a corresponding debugger to the debugger server. The debugger server coordinates the run mode of the debugger adapters. Each debugger adapter controls the run mode of its corresponding debugger. | 08-15-2013 |
20140196014 | System and Method of Debugging Multi-Threaded Processes - A system and method of debugging a multi-threaded process with at least one running thread and at least one suspended thread is disclosed. Embodiments utilize a blocking function to block the thread of a process while other threads are allowed to run. The blocking function may be executed in a suspended thread by a debugger under control of a thread blocking controller. The other threads may implement interprocess communication channels for enabling communication between the process and another application. A simulated user interface (UI) of a debugger enables interaction with users while a hardware simulation thread is blocked, where blocking of the hardware simulation thread may be implemented by a thread blocking component implemented externally to the debugger. Where a thread blocking controller is implemented within the debugger, a debugger UI may interact with a user while the hardware simulation thread is blocked and interprocess communication threads are running | 07-10-2014 |
20150058854 | Direct Memory Interface Access in a Multi-Thread Safe System Level Modeling Simulation - Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process. | 02-26-2015 |
Patent application number | Description | Published |
20150326069 | Enhanced Receiver for Wireless Power Transmission - An enhanced receiver for wireless power transmission is disclosed. The receiver may be able to convert RF waves into continuous, stable and suitable voltage or power that can be used for charging or powering an electronic device. The receiver may include an antenna array for extracting and rectifying power from RF waves or pockets of energy. An input boost converter in the receiver may step up and stabilize the rectified voltage, while charging a storage element in the receiver. An output boost converter in the receiver may step up the output voltage of the storage element to deliver continuous and suitable power or voltage to a load. A microcontroller in the receiver may perform power measurements at different nodes or sections to adjust the operation of the input and output boost converters so that load power requirements can be satisfied at all times. | 11-12-2015 |
20150326070 | Methods and Systems for Maximum Power Point Transfer in Receivers - A MPPT management method in a receiver used for wireless power transmission may include the monitoring of the power extracted from RF waves at a dedicated antenna element in the receiver; detecting MPPT at an intelligent input boost converter in the receiver; comparing the detected MPPT with MPPT tables stored or calculated within a main system micro-controller in the receiver; adjusting the MPPT at the intelligent boost converter to find a suitable maximum peak that may enable an optimal power extraction from RF waves. | 11-12-2015 |
20150326072 | Boost-Charger-Boost System for Enhanced Power Delivery - A controlled-power delivery system may operate with RF waves for supplying continuous and suitable power to a load. The controlled-power delivery system may include one or more receiving antennas, one or more rectifiers, a first boost converter, a charger, a storage element, and a second boost converter. The first boost converter may step up the rectified DC voltage obtained from the receiving antenna and rectifier to supply a suitable voltage level that can be used for charging the storage element. The second boost converter may increase the voltage from the storage element to a suitable level that may satisfy the power requirements of the load. The charger in conjunction with the first and second boost converters may be configured to allow a plurality of modes of operation for delivering power to the load and charging the storage element. | 11-12-2015 |
20150326142 | Integrated Rectifier and Boost Converter for Wireless Power Transmission - A novel integrated rectifier and boost converter circuit architecture is disclosed. The rectifier architecture includes a plurality of identical half-bridge rectifiers connected to receiving antennas to convert wireless AC power into DC power. The integrated rectifier may be coupled in series with a charging inductor in a boost converter. The inductor may discharge upon operation of two micro-controller-driven switching transistors using predetermined threshold and timing scheme to turn on/off. The rectifier architecture may provide high power densities, improve efficiency at larger load currents, and may be enabled in an integrated circuit with eight RF signal inputs, eight half-bridge rectifiers, and eight DC outputs ganged together as single feed into the boost converter. The rectifier circuit topology may include a comparator driven by the boost controller with a proprietary algorithm which suits control for a maximum power point tracking functionality, and an external micro-controller for additional control of the boost converter. | 11-12-2015 |
20150326143 | Synchronous Rectifier Design for Wireless Power Receiver - Synchronous rectifier circuit topologies for a wireless power receiver receiving a supply of power from a wireless transmitter are disclosed. The synchronous rectifier circuit topologies include a half-bridge diode-FET transistor rectifier for rectifying the wireless power into power including a DC waveform, using a control scheme that may be provided by a delay-locked loop clock, or phase shifters, or wavelength links to control conduction of FET transistors in the synchronous rectifier circuit topology, and maintaining a constant switching frequency to have the diodes, coupled to FET transistors, to allow current to flow through each one respectively at the appropriate timing, focusing on high conduction times. The synchronous rectifier circuit topologies may enable power transfer of high-frequency signals at enhanced efficiency due to significant reduction of forward voltage drop and lossless switching. | 11-12-2015 |
20150340910 | Enhanced Transmitter for Wireless Power Transmission - An enhanced transmitter for wireless power transmission is disclosed. The transmitter may be able to transmit radio frequency (RF) waves or pockets of energy for charging or powering an electronic device. The transmitter may include antenna element arrangements for receiving RF waves from a plurality of wireless sources and process them using a dedicated RF integrated circuit (RFIC) and set of antenna elements for receiving RF input signals from a plurality of wireless power sources. A digital signal processor (DSP) may be used to control reception using the dedicated RFIC and antenna elements of reception and to control transmission of wireless power selecting the transmitting RFICs and configuration of antenna elements to send RF waves or pockets of energy to a wireless receiver. The frequency of RF waves received may be sampled through a down converter array and line addressing devices to send the signals received to a micro-controller including a proprietary algorithm which control switching and processing necessary for faster and enhanced wireless power transmission, thus improving transmission efficiency. | 11-26-2015 |
Patent application number | Description | Published |
20100026162 | FIXING MECHANISM FOR AN INNER ASSEMBLY TO OUTER BULB - A lamp assembly includes an inner assembly that has a CFL source, an electronics board, and a holder that interconnects the CFL source and electronics board. An outer, light transmissive envelope surrounds the inner assembly and various fixing arrangements are disclosed for securing the inner assembly to the outer envelope. Three primary mechanisms are a ratchet mechanism, a spring mechanism, or using adhesive to secure the inner assembly to the outer envelope under a predetermined tension. | 02-04-2010 |
20120007486 | LED LIGHT SOURCE IN INCANDESCENT SHAPED LIGHT BULB - An LED light bulb that includes a base providing an electrical connector and a substantially hollow envelope extending from the base. The light bulb further includes a metal space separator having a top side, bottom side and side wall that has a plurality of holes connected by at least one channel that extends through the interior of the separator, such that air can pass through the separator. At least one LED is mounted on the separator in electrical connection with the base connector. | 01-12-2012 |
20120104965 | CURRENT RINGING FILTER FOR DIMMABLE COMPACT FLUORESCENT LAMPS - A ballast or drive circuit is located between a dimmer switch and at least one light source or lamp. The ballast includes an electromagnetic interference (EMI) filter operatively disposed between the dimmer switch and the at least one lamp. The EMI filter includes an inductor. A low pass filter, preferably an inductor, is serially connected to the inductor of the EMI filter and situated between the dimmer switch and EMI filter for addressing currency ringing, reducing high current peaks, and decreasing flickering that would otherwise result with multiple light sources when the lamp is turned on. | 05-03-2012 |
20140175980 | SYSTEM AND METHOD FOR IMPROVED RAPID CYCLING PERFORMANCE OF INSTANT START FLUORESCENT LAMPS - Provided is a system for improving rapid cycling performance of instant start compact self-ballasted fluorescent lamps. The system provides a ballast driver circuit including a lamp driver, a lamp voltage detector, an additional cathode heating driver, and a wire lamp. The additional cathode heating driver applies an additional amount of current to the cathodes of the wire lamp during the glow phase after the ignition of the lamp. | 06-26-2014 |
Patent application number | Description | Published |
20110286499 | Reduced Complexity Channel Estimation for Uplink Receiver - The present invention proposes an LTE eNodeB receiver channel estimation technique that is referred to as reduced complexity minimum mean squared error (MMSE) technique for channel estimation. From the invention's assumptions, estimations and modified calculations, the present invention generates precise channel estimates of RS using the reduced complexity MMSE matrix and previously computed LS channel estimates H | 11-24-2011 |
20110293028 | METHOD AND SYSTEM FOR REDUCED COMPLEXITY CHANNEL ESTIMATION AND INTERFERENCE CANCELLATION FOR V-MIMO DEMODULATION - A method and system for wireless communication in a wireless communication network. The wireless communication network has a first mobile terminal and a second mobile terminal arranged in virtual multiple input, multiple output (“V-MIMO”) communication with a base station. A first wireless communication uplink channel corresponding to the first mobile terminal is estimated. The estimate is based on a first reference symbol signal and the cancellation of interference from a second reference symbol signal received from the second mobile terminal. A second wireless communication uplink channel corresponding to the second mobile terminal is estimated. The estimate is based on the second reference symbol signal and the cancellation of interference from the first reference symbol signal received from the first mobile terminal. The estimated first wireless communication uplink channel is used to demodulate a first data signal received from the first wireless device, and the estimated second wireless communication uplink channel is used to demodulate a second data signal received from the second wireless device. | 12-01-2011 |
20130182746 | Reduced Complexity Channel Estimation for Uplink Receiver - The present invention proposes an LTE eNodeB receiver channel estimation technique that is referred to as reduced complexity minimum mean squared error (MMSE) technique for channel estimation. From the invention's assumptions, estimations and modified calculations, the present invention generates precise channel estimates of RS using the reduced complexity MMSE matrix and previously computed LS channel estimates H | 07-18-2013 |
20140211741 | Channel Estimation and Interference Cancellation for Virtual MIMO Demodulation - A method and system for wireless communication in a wireless communication network. The wireless communication network has a first mobile terminal and a second mobile terminal arranged in virtual multiple input, multiple output (“V-MIMO”) communication with a base station. A first wireless communication uplink channel corresponding to the first mobile terminal is estimated. The estimate is based on a first reference symbol signal and the cancellation of interference from a second reference symbol signal received from the second mobile terminal. A second wireless communication uplink channel corresponding to the second mobile terminal is estimated. The estimate is based on the second reference symbol signal and the cancellation of interference from the first reference symbol signal received from the first mobile terminal. The estimated first wireless communication uplink channel is used to demodulate a first data signal received from the first wireless device, and the estimated second wireless communication uplink channel is used to demodulate a second data signal received from the second wireless device. | 07-31-2014 |
20150016348 | PREDICTABLE SCHEDULER FOR INTERFERENCE MITIGATION - A method and apparatus assigning Physical Resource Blocks, PRBs, to a User Equipment, UE, in a wireless communication network having a plurality of cells, includes determining a Physical Cell Identifier, PCI, of a cell from the plurality of cells. Selecting a power level pattern of multiple PRBs for allocation, and assigning at least one of the multiple PRBs to the UE. | 01-15-2015 |
20150280941 | Channel Estimation and Interference Cancellation for Virtual MIMO Demodulation - A method and system for wireless communication in a wireless communication network. The wireless communication network has a first mobile terminal and a second mobile terminal arranged in virtual multiple input, multiple output (“V-MIMO”) communication with a base station. A first wireless communication uplink channel corresponding to the first mobile terminal is estimated. The estimate is based on a first reference symbol signal and the cancellation of interference from a second reference symbol signal received from the second mobile terminal. A second wireless communication uplink channel corresponding to the second mobile terminal is estimated. The estimate is based on the second reference symbol signal and the cancellation of interference from the first reference symbol signal received from the first mobile terminal. The estimated first wireless communication uplink channel is used to demodulate a first data signal received from the first wireless device, and the estimated second wireless communication uplink channel is used to demodulate a second data signal received from the second wireless device. | 10-01-2015 |
Patent application number | Description | Published |
20100105168 | MICROELECRONIC ASSEMBLY AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. First and second substrates ( | 04-29-2010 |
20100127345 | 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES | 05-27-2010 |
20100127394 | THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming ( | 05-27-2010 |
20100264548 | THROUGH SUBSTRATE VIAS - Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region ( | 10-21-2010 |
20110156266 | METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit. | 06-30-2011 |
20110272823 | THROUGH SUBSTRATE VIAS - Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5. | 11-10-2011 |
20120037969 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates ( | 02-16-2012 |
20130143367 | METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES - Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing. | 06-06-2013 |
20140332980 | METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES - Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing. | 11-13-2014 |
20150228545 | METHODS OF MAKING A MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face ( | 08-13-2015 |
20160049508 | BIDIRECTIONAL TRENCH FET WITH GATE-BASED RESURF - A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage. | 02-18-2016 |