Patent application number | Description | Published |
20090003050 | FLOATING BODY MEMORY ARRAY - Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells. | 01-01-2009 |
20090146208 | Independently controlled, double gate nanowire memory cell with self-aligned contacts - A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used. | 06-11-2009 |
20090159975 | INTEGRATION OF PLANAR AND TRI-GATE DEVICES ON THE SAME SUBSTRATE - An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed. | 06-25-2009 |
20100006941 | Intergration of a floating body memory on soi with logic transistors on bulk substrate - A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon. | 01-14-2010 |
20100297838 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 11-25-2010 |
20120267721 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 10-25-2012 |
20130009248 | INDEPENDENTLY ACCESSED DOUBLE-GATE AND TRI-GATE TRANSISTORS IN SAME PROCESS FLOW - A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device. | 01-10-2013 |
20140177625 | ELECTRO-OPTICAL ASSEMBLY INCLUDING A GLASS BRIDGE - Embodiments of the present disclosure provide techniques and configurations for routing signals of an electro-optical assembly using a glass bridge. In one embodiment, an electro-optical assembly includes a laser die having a laser device and a glass bridge electrically coupled with the laser die by one or more interconnect structures, the glass bridge including electrical routing features configured to route electrical signals to the laser die from a transmitter device. Other embodiments may be described and/or claimed. | 06-26-2014 |
20140334768 | LOW COST INTEGRATION OF OPTICAL COMPONENTS IN PLANAR LIGHTWAVE CIRCUITS - Planar lightwave circuits with a polymer coupling waveguide optically coupling a planar waveguide over a first region of a substrate to an optical component, such as a laser, affixed to a second region of the substrate. The coupling waveguide may be formed from a polymer layer applied over the planar waveguide and optical component such that any misalignment between the two may be accommodated by patterning the polymer into a waveguide having a first end aligned to an end of the planar waveguide and a second end aligned to an edge of the optical component. In embodiments, the polymer is photo-definable, such as a negative resist, and may be patterned through direct laser writing. In embodiments, the optical component is a thin film affixed to the substrate through micro-transfer printing. In other embodiments, the optical component is a semiconductor chip affixed to the substrate by flip-chip bonding. | 11-13-2014 |