Patent application number | Description | Published |
20100107037 | MEMORY SYSTEM WITH ERROR CORRECTION AND METHOD OF OPERATION - A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory. | 04-29-2010 |
20130111195 | DATA PROCESSING SYSTEM WITH SAFE CALL AND RETURN | 05-02-2013 |
20130138930 | COMPUTER SYSTEMS AND METHODS FOR REGISTER-BASED MESSAGE PASSING - Systems and methods are disclosed that include a plurality of processing units having a plurality of register file entries. Control logic identifies a first register entry as including a message address in response to receiving a first instruction. The control logic further identifies a second register entry to receive messages in response to receiving a second instruction. | 05-30-2013 |
20140189244 | SUPPRESSION OF REDUNDANT CACHE STATUS UPDATES - A cache management system employs a replacement policy in a manner that manages redundant accesses to cache elements. The cache management system comprises a cache, a replacement policy state storage and an update control module. The update control module comprises a buffer for storing recent addresses, a comparison unit for comparing a new address with those stored in the recent address buffer, and an update unit which determines whether to update the replacement policy state storage. When an address matches those stored in the recent address buffer, a replacement status update is suppressed. | 07-03-2014 |
20140259149 | PROGRAMMABLE DIRECT MEMORY ACCESS CHANNELS - A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device. | 09-11-2014 |
20140282564 | THREAD-SUSPENDING EXECUTION BARRIER - An energy-efficient execution barrier for parallel processing is provided. The execution barrier associates a thread-execution bit with each hardware-supported thread. The energy-efficient execution barrier utilizes a per-processor or per-chip bit vector register, having, for example, one bit per possible thread. A bit enables or disables the execution of its corresponding thread. A process starts by forking threads and enabling them in the bit vector register. When a thread arrives at the barrier/rendezvous, the thread disables its own bit and therefore suspends thread execution. When a distinguished thread arrives at the barrier, it waits (e.g., spinlocks) until all the threads needed for the rendezvous are disabled. The distinguished thread (or an automatic thread re-enable mechanism) then atomically sets all threads bits in the bit vector register to enabled, and the threads perform any appropriate sync operations and continue. | 09-18-2014 |
20140321185 | FOUR PORT MEMORY WITH MULTIPLE CORES - A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks. | 10-30-2014 |
20150046658 | CACHE ORGANIZATION AND METHOD - A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced. | 02-12-2015 |