| Patent application number | Description | Published |
|---|
| 20080213959 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield - An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced. | 09-04-2008 |
| 20090032814 | SiGe DIAC ESD protection structure - A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors. | 02-05-2009 |
| 20090038142 | METHODS OF FORMING INDUCTORS ON INTEGRATED CIRCUITS - The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the forming of a metal seed layer, the deposition and patterning of photoresist, the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements. | 02-12-2009 |
| 20090040000 | INTEGRATED CIRCUITS WITH INDUCTORS - The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes. | 02-12-2009 |
| 20090091414 | On-chip inductor for high current applications - Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications. | 04-09-2009 |
| 20090096548 | Tuning and compensation technique for semiconductor bulk resonators - One or more pn junctions are provided on the resonating bar of a semiconductor bulk resonator. When a reverse bias is imposed upon the pn junction(s), a variable depletion layer results and, hence, capacitance. The depletion layer capacitance allows for variable coupling to the resonator bar. The variable coupling allows control circuitry to null out or compensate for variation related to temperature and/or drift. | 04-16-2009 |
| 20090116269 | Power supply with reduced power consumption when a load is disconnected from the power supply - Detection and control circuitry are added to a conventional power supply to detect when a load, such as a portable electronic device, has been disconnected from the power supply and, when disconnected, interrupt a current path to the primary windings of a transformer within the power supply to substantially reduce the amount of reactive power that is consumed by the power supply. | 05-07-2009 |
| 20090144035 | Black box model for large signal transient integrated circuit simulation - A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis. | 06-04-2009 |
| 20090160592 | Helical core on-chip power inductor - An on-chip inductor structure includes a conductive inductor coil and a helical ferromagnetic inductor core that is formed to wrap around the conductive coil. The coil is space-apart from the ferromagnetic core by intervening dielectric material. The helical core structure includes at least one magnetic gap lithographically formed in the core. | 06-25-2009 |
| 20090162978 | Method of Forming a SiGe DIAC ESD Protection Structure - A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors. | 06-25-2009 |
| 20090256687 | MAGNETIC FIELD GUARD RINGS - A magnetic guard ring is provided to reduce the susceptibility of a transformer-based data transmission to an externally generated magnetic field. The guard ring structure comprises strategically placed pieces of ferrite material, such as NiFe, that surround the transformer and “steer” the external magnetic field away from the transformer. | 10-15-2009 |
| 20090296493 | MID-SIZE NVM CELL AND ARRAY UTILIZING GATED DIODE FOR LOW CURRENT PROGRAMMING - A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided. | 12-03-2009 |
| 20100001365 | ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP - An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk. | 01-07-2010 |
| 20100068864 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils. | 03-18-2010 |
| 20100140663 | CMOS Compatable fabrication of power GaN transistors on a <100> silicon substrate - In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor. | 06-10-2010 |
| 20100141292 | Method and system for measuring film stress in a wafer film - In a MEMS wafer, film stresses are measured by placing an inductor array over or under the wafer and measuring inductance variations across the array to obtain a map defining the amount of bowing of the wafer. | 06-10-2010 |
| 20100141374 | Transformer with signal immunity to external magnetic fields - In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a | 06-10-2010 |
| 20100142239 | Fully integrated multi-phase grid-tie inverter - In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase. | 06-10-2010 |
| 20100144116 | Method of forming high lateral voltage isolation structure involving two separate trench fills - In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench. | 06-10-2010 |
| 20100215995 | MAGNETIC STATE OF CHARGE SENSOR FOR A BATTERY - A battery includes multiple conductive battery plates and a complex electrolytic material located between the conductive battery plates. The battery also includes a conductive sensor wire located within the complex electrolytic material. The conductive sensor wire may be configured to generate a magnetic field within the complex electrolytic material based on an electrical signal flowing through the conductive sensor wire. The battery may further include a temperature sensor wire within the complex electrolytic material. | 08-26-2010 |
| 20100295550 | ADAPTIVE ENERGY MANAGEMENT TERMINAL FOR A BATTERY - A battery includes multiple conductive plates and a permeable electrolytic material and an ion membrane located between the conductive plates. The battery also includes at least one wire located within one or more of the permeable electrolytic material and the ion membrane. The at least one wire can be configured to regulate a flow of ions through the ion membrane based on an electrical signal flowing through the at least one wire. The at least one wire could also be configured to generate a magnetic field within the permeable electrolytic material based on another electrical signal flowing through the at least one wire. The battery could further include a temperature sensor wire within the permeable electrolytic material. | 11-25-2010 |
| 20100295638 | METHOD OF SWITCHING A MAGNETIC MEMS SWITCH - A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators. | 11-25-2010 |
| 20110007570 | METHOD OF READING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time. | 01-13-2011 |
| 20110007574 | METHOD OF ERASING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time. | 01-13-2011 |
| 20110025443 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure. | 02-03-2011 |
| 20110084607 | Integrated driver system architecture for light emitting diodes (LEDS) - A method includes forming one or more capacitors over a substrate. The method also includes forming a transformer at least partially over the substrate. The transformer is adjacent to at least one of the one or more capacitors. At least a portion of the transformer is formed at a same level over the substrate as the one or more capacitors. The method further includes coupling the one or more capacitors and the transformer to at least one embedded integrated circuit die. The one or more capacitors, the transformer, and the at least one embedded integrated circuit die form at least part of a light emitting diode (LED) driver. | 04-14-2011 |
| 20110095365 | Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method - A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device. | 04-28-2011 |
| 20110118607 | SELF-PROPELLED ROBOTIC DEVICE THAT MOVES THROUGH BODILY AND OTHER PASSAGEWAYS - A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder. | 05-19-2011 |
