Patent application number | Description | Published |
20120306926 | INLINE SCALING UNIT FOR MIRROR MODE - A scaling unit is disclosed that is within a computing device having an internal display and an external interface. The scaling unit facilitates the concurrent presentation of images on the internal display and an external display connected to the external interface. In configurations in which the external interface does not have sufficient data width to concurrently display images on the external display at the same resolution as the internal display, the scaling unit may be used to reduce the number of pixels in a line, thus reducing bandwidth requirements at the external interface. The scaling unit may also scale further to maintain an aspect ratio of the image displayed on the internal display. Further vertical scaling may be performed outside the computing device (e.g., by a dongle coupled between the computing device and the external display), such that the scaling unit may be implemented with reduced memory requirements. | 12-06-2012 |
20120307141 | FRAME RETIMING FOR MIRROR MODE - An inline scaling unit configured to retime an input video frame is disclosed. The scaling unit is configured to receive pixels within a line of a video frame to be displayed on a primary display that is within a first clock domain. The scaling unit down-scales the group of pixels and writes the down-scaled pixels to a buffer circuit in the first clock domain. The scaling unit includes a control circuit configured to generate horizontal and vertical control signals for the retimed video frame to be displayed on a secondary display that is within a second clock domain. The horizontal and vertical control signals are then used to enable reading from the buffer circuit in the second clock domain. The scaling unit outputs the down-scaled pixels and the generated control signals within the retimed video frame such that input video frame and the retimed video frame may be displayed concurrently. | 12-06-2012 |
20130057567 | Color Space Conversion for Mirror Mode - The same pixel stream may be displayed on an internal display and an external display while maintaining the original aspect ratio corresponding to the internal display dimensions. A connector with limited number of pins may only support a two-wire display port interface to the external display, which may not provide enough bandwidth to transmit the full resolution image to the external display. To transmit the full resolution image, a color space conversion from RGB space to YCbCr color space may be performed. The Luma component may be transmitted at full resolution, while the chroma components may be scaled. Accordingly, there is no loss of image resolution, while some amount of color resolution may be lost. However, there is no need to retime frames within the system on chip (SOC), and the same pixel stream may be used as the basis for display on both the internal and the external display. | 03-07-2013 |
20140071140 | DISPLAY PIPE REQUEST AGGREGATION - A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode. | 03-13-2014 |
20140075117 | DISPLAY PIPE ALTERNATE CACHE HINT - A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache. | 03-13-2014 |
20140085320 | EFFICIENT PROCESSING OF ACCESS REQUESTS FOR A SHARED RESOURCE - A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests. | 03-27-2014 |
20140089604 | BIPOLAR COLLAPSIBLE FIFO - A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared buffer accessed by two requestors generating access requests. Any entry within the shared buffer may be allocated for use by a first requestor or a second requestor. The storage buffer stores received indications of access requests from the first requestor beginning at a first end of the storage buffer. The storage buffer stores received indications of access requests from the second requestor beginning at a second end of the storage buffer. The storage buffer maintains an oldest stored indication of an access request for the first requestor at the first end and an oldest stored indication of an access request for the second requestor at the second end. The shared buffer deallocates in-order of age from oldest to youngest allocated entries corresponding to a given requestor of the first requestor and the second requestor. | 03-27-2014 |
20140204100 | Modified Quality of Service (QoS) Thresholds - In an embodiment, a display pipe processes video data for visual display. The display pipe may read the video data from memory, and may employ QoS levels with the memory requests to ensure that enough data is provided to satisfy the real time display requirements. The display pipe may include a pixel buffer that stores pixels that are ready for display. Additionally, the display pipe may include one or more input buffers configured to store input video data to be processed and/or one or more output buffers configured to store processed data that is ready for blending into the final pixels for display. The display pipe determine a number of output equivalent pixels in the data in the input and output buffers, and may consider those pixels as well as the ready pixels in the pixel buffer in determining the QoS levels for requests. | 07-24-2014 |
20140237195 | N-DIMENSIONAL COLLAPSIBLE FIFO - A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared data structure accessed by multiple requestors. Both indications of access requests and indices pointing to entries within the data structure are stored in storage buffers. Each storage buffer maintains at a selected end an oldest stored indication of an access request from a respective requestor. Each storage buffer stores information for the respective requestor in an in-order contiguous manner beginning at the selected end. The indices stored in a given storage buffer are updated responsive to allocating new data or deallocating stored data in the shared data structure. Entries in a storage buffer are deallocated in any order and remaining entries are collapsed toward the selected end to eliminate gaps left by the deallocated entry. | 08-21-2014 |
20140240332 | Multiple Quality of Service (QoS) Thresholds or Clock Gating Thresholds Based on Memory Stress Level - In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller. | 08-28-2014 |
20140253570 | Network Display Support in an Integrated Circuit - In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation. | 09-11-2014 |
20140292787 | Compressed Frame Writeback and Read for Display in Idle Screen On Case - In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content. | 10-02-2014 |
20140292788 | Mechanism to Detect Idle Screen On - In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content. | 10-02-2014 |
20140333643 | INVERSE REQUEST AGGREGATION - A system and method for efficiently scheduling memory access requests from a display controller pipeline. The display controller monitors the amount of data in the line buffers in the internal pixel-processing pipelines. The display controller waits until the amount of data in a given line buffer has fallen below an amount equal to the pixel width of the region being rendered by the internal pixel-processing pipeline before issuing memory requests to the memory controller. When the memory controller is not processing received memory requests, the memory controller transitions to a low-power state. | 11-13-2014 |
20150042659 | VIDEO DATA COMPRESSION FORMAT - A method and device for data compression are presented, in which a data processor may receive a packet of image data which includes four groups of N bits, where N is an integer greater than 2. The data processor may compress the received packet of data, such that a total number of bits for the converted packet is less than four times N. The data processor may compress the received packet of image data by reducing the resolution of three of the values while maintaining the resolution of the fourth value. To reduce the resolution of the three values, the data processor may apply a dithering formula to the values. The data processor may then send the converted packet via an interface. | 02-12-2015 |
20150062134 | PARAMETER FIFO FOR CONFIGURING VIDEO RELATED SETTINGS - A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve a top frame packet from the parameter buffer and determine if the frame packet is an internal type, i.e., intended for internal registers in a respective processing unit or if it is an external type, i.e., intended for an external register elsewhere in the graphics system. Based on the type of frame packet, the control circuit may update one or more register values accordingly. | 03-05-2015 |
20150070365 | ARBITRATION METHOD FOR MULTI-REQUEST DISPLAY PIPELINE - Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request. | 03-12-2015 |