Patent application number | Description | Published |
20080220545 | SYSTEM AND METHOD FOR TESTING AND PROVIDING AN INTEGRATED CIRCUIT HAVING MULTIPLE MODULES OR SUBMODULES - In an integrated circuit having a plurality of modules and/or submodules that each perform a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or submodule is compared with the test signature and defective modules to identify defective modules and/or submodules. The identity of defective modules/submodules is stored on the integrated circuit for subsequent use by a customer. Integrated circuits having one or more defective modules/submodules are sold to customers with full disclosure of which modules/submodules are defective, thereby improving the yield associated with the product. Pricing of the product is discounted for products with less than full functionality. | 09-11-2008 |
20080246341 | POWER SUPPLY SELECTION FOR MULTIPLE CIRCUITS ON AN INTEGRATED CIRCUIT - An integrated circuit comprising a plurality of circuits is provided. The integrated circuit further comprises a plurality of power circuits, wherein each of the plurality of power circuits can supply a selected voltage to at least one of the plurality of circuits. | 10-09-2008 |
20090196086 | HIGH BANDWIDTH CACHE-TO-PROCESSING UNIT COMMUNICATION IN A MULTIPLE PROCESSOR/CACHE SYSTEM - A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set. | 08-06-2009 |
20090263138 | FREE-SPACE OPTICAL COMMUNICATION SYSTEM - A free-space communication system and method of operation includes a first communication device physically coupled to a substrate and having an optical transmitter for communicating information. A second communication device is physically coupled to the substrate and has an optical receiver for communicating information. An adjustable optical beam deflector is physically coupled to the substrate for optically coupling the first communication device and the second communication device via an optical beam including a free-space optical portion. A feedback system includes a non-optical communication link for receiving information regarding the optical beam. The feedback system controls the adjustable optical beam deflector to direct the optical beam to improve the quality of an optical link incorporating the optical beam. At least one sensor is physically coupled to the substrate for monitoring one or more environmental conditions and providing information of the one or more environmental conditions to the feedback system. | 10-22-2009 |
20090263143 | OPTICAL COMMUNICATION INTEGRATION - An integrated circuit die has a transistor circuitry section for implementing information handling operations. Optical circuitry is within the single semiconductor die. The optical circuitry includes a laser transmitter and is operably coupled to the transistor circuitry section. The transistor circuitry section originates information. The optical circuitry transmits the information in a laser beam through a wave guide to the edge of the integrated circuit die. | 10-22-2009 |
20100308900 | METHOD AND CIRCUIT FOR CHARGING AND DISCHARGING A CIRCUIT NODE - A voltage circuit and method charges a circuit node to a first predetermined voltage. The first predetermined voltage charged onto the circuit node is used for a first predetermined function during a first time period. A portion of charge from the circuit node is removed to circuitry coupled to the circuit node. The portion of the charge is reused during a second time period subsequent to the first time period. In one form a voltage generator has diode configurable transistors for passing current in only one direction depending upon whether the circuit node is being charged or discharged. In another form a switch couples the circuit node between a reference terminal and another circuit for charge reuse. Reuse of charge permits increased power savings. | 12-09-2010 |
20110032026 | VOLTAGE BOOSTING SYSTEM WITH SLEW RATE CONTROL AND METHOD THEREOF - A system includes a voltage controlled oscillator, a charge pump, and a current regulator circuit. The voltage controlled oscillator has a control input and a clock output that provides a clock signal at a clock frequency that is variable. The charge pump is coupled to the clock output and has an output that provides a boosted output voltage. The current regulator circuit is coupled to the control input of the voltage controlled oscillator to adjust the clock frequency based on a simulation of a rate of change of the boosted output voltage. This allows for a controlled slew rate for the output of the charge pump. | 02-10-2011 |
20110057306 | EDGE MOUNTED INTEGRATED CIRCUITS WITH HEAT SINK - A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge and electronic circuits having ports on the second edge. The second edges are connected to the substrate. The first major surface of the second integrated circuit is parallel with the second major surface of the first integrated circuit. The heat sink has a backplane adjacent to the third edge, a first portion along the first major surface of the first integrated circuit, a second portion along the second major surface of the second integrated circuit extending from the backplane, and an insert between the first major surface of the second integrated circuit and the second major surface of the first integrated circuit. | 03-10-2011 |
20110115550 | SYSTEM AND METHOD FOR COMMUNICATING BETWEEN MULTIPLE VOLTAGE TIERS - A system includes first, second, and third circuits and first and second capacitors. The first capacitor has a first power supply terminal coupled to positive power supply terminal, a second power supply terminal, and an input/output. The second capacitor has a first power supply terminal coupled the second power supply terminal of the first circuit, a second power supply terminal, and an input/output. The third circuit has a first power supply terminal coupled the second power supply terminal of the second circuit, a second power supply terminal, and an input/output. The first capacitor has a first terminal coupled to the input/output of the first circuit and a second terminal coupled to the input/output of the second circuit. The second capacitor has a first terminal coupled to the second terminal of the first capacitor and a second terminal coupled to the input/output of the third circuit. | 05-19-2011 |
20110115554 | SYSTEM HAVING MULTIPLE VOLTAGE TIERS AND METHOD THEREFOR - A system includes a first circuit, a first charge pump, a second circuit, and a second charge pump. The first circuit has a first power supply terminal coupled to a positive power supply terminal and a second power supply terminal. The first charge pump has an input coupled to positive power supply terminal and an output coupled to the second power supply terminal of the first circuit. The second circuit has a first power supply terminal coupled the second power supply terminal of the first circuit and a second power supply terminal. The second charge pump has an input coupled to the first power supply terminal of the second circuit and an output coupled to the second power supply terminal of the second circuit. | 05-19-2011 |
20120069636 | STATIC RANDOM ACCESS MEMORY (SRAM) HAVING BIT CELLS ACCESSIBLE BY SEPARATE READ AND WRITE PATHS - A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of the first plurality of bit cells includes a cross coupled pair of inverters for storing a logic state, optimized for being written, and powered by a read voltage during a read of the first plurality of bit cells. Each bit cell of the first plurality of bit cells is coupled to a true read bit line and a true write bit line, and a second plurality of bit cells is coupled to a complementary read bit line and a complementary write bit line. The true and complementary read bit lines are precharged to a precharge voltage of about half the read voltage. The true read bit line is predisposed to a logic low condition. One of a group consisting of a high impedance from the first bit cell to indicate that the logic state is a logic low and a signal voltage greater than the intermediate voltage to indicate that the logic state is a logic high is output from the first bit cell to the true read bit line. | 03-22-2012 |
20120092917 | ROM MEMORY DEVICE - A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage. | 04-19-2012 |
20130087926 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device. | 04-11-2013 |
20130088255 | STACKED SEMICONDUCTOR DEVICES - A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device. | 04-11-2013 |
20130181350 | SEMICONDUCTOR DEVICES WITH NONCONDUCTIVE VIAS - An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures. | 07-18-2013 |
20130235686 | BIPOLAR PRIMARY SENSE AMPLIFIER - A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a read cycle. The sense amplifier has a feedback circuit that couples the collector of one of the bi polar transistors to the base of the other bipolar transistor and vice versa. | 09-12-2013 |
20130320480 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES - A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate. | 12-05-2013 |
20130322159 | MULTI-PORT REGISTER FILE WITH MULTIPLEXED DATA - A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal. | 12-05-2013 |
20140001641 | METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES | 01-02-2014 |
20140015061 | METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES - A memory device includes a storage unit formed using a substrate, a true bit line BL | 01-16-2014 |
20140016400 | WORD LINE DRIVER CIRCUITS AND METHODS FOR SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE - A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN). | 01-16-2014 |
20140016402 | SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE - An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations. | 01-16-2014 |
20140071652 | TECHNIQUES FOR REDUCING INDUCTANCE IN THROUGH-DIE VIAS OF AN ELECTRONIC ASSEMBLY - An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly. | 03-13-2014 |
20140197541 | MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE - A microelectronic assembly ( | 07-17-2014 |
20140197871 | TRANSMISSION SYSTEM - A signal transmission system ( | 07-17-2014 |
20140197976 | BUS SIGNAL ENCODED WITH DATA AND CLOCK SIGNALS - A CODEC includes a transmission path between an encoder and a decoder. The encoder receives bits of data in a first form in which each bit of the data is represented by switching between first and second logic states and no voltage change between consecutive bits of the same logic state and serially transmits the bits in a second form in which the first logic state is maintained at a high voltage, the second logic state is maintained at a low voltage, and an intermediate voltage is maintained between consecutive bits. The decoder receives the bits in the second form and derives a clock from the occurrences of the intermediate voltage. The clock, repetitively, is maintained at a logic high, then switches directly from the logic high to a logic low, then is maintained at the logic low, and then switches directly between the logic low and the logic high. | 07-17-2014 |
20140198561 | MULTIPORT MEMORY WITH MATCHING ADDRESS AND DATA LINE CONTROL - In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to the first bit line pair via second switching logic and to the second bit line pair via third switching logic. If a row address match but not a column address match exists between a first and second access address, the second switching logic selectively connects the second data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair. | 07-17-2014 |
20140198590 | MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL - In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair. | 07-17-2014 |
20140203841 | Systems And Methods For Reduced Coupling Between Digital Signal Lines - Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations. | 07-24-2014 |
20140241100 | SYNCHRONOUS MULTIPLE PORT MEMORY WITH ASYNCHRONOUS PORTS - A memory system includes a multi-port memory having a first port and a second port. First registers and second registers provide first and second addresses, respectively, to the first and second ports. An access controller controls the multi-port memory to launch an access for the valid address provided by the first input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the first clock and to launch an access for the valid address provided by the second input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the second clock. | 08-28-2014 |
20140252487 | Gate Security Feature - An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., | 09-11-2014 |
20140269016 | MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL - A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to the second port switching to the same address as the first port to make a row match, the second port and the first port use the first plurality of word lines, but the first port uses the first plurality of bit lines and the second port uses the second plurality of bit lines. If the row match is removed by the first port changing row addresses, a correlation swap is performed so that the first port performs accesses using the second word lines and bit lines and the second port performs accesses using the first word lines and bit lines. | 09-18-2014 |
20140321185 | FOUR PORT MEMORY WITH MULTIPLE CORES - A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks. | 10-30-2014 |
20140362425 | Communication System Die Stack - A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks ( | 12-11-2014 |
20140363119 | Integration of a MEMS Beam with Optical Waveguide and Deflection in Two Dimensions - A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a plurality of deflectable MEMS optical beam waveguides (e.g., | 12-11-2014 |
20140363120 | Optical Backplane Mirror - An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer ( | 12-11-2014 |
20140363124 | Optical Redundancy - A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a first integrated circuit link element ( | 12-11-2014 |
20140363153 | Optical Die Test Interface - An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures ( | 12-11-2014 |
20140363172 | Die Stack with Optical TSVs - A high density, low power, high performance information system, method and apparatus are described in which a laser source ( | 12-11-2014 |
20140363905 | Optical Wafer and Die Probe Testing - An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die ( | 12-11-2014 |
20150054562 | LEVEL SHIFTER WITH STATIC PRECHARGE CIRCUIT - A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage. During an evaluate phase, the level shifter maintains one of the nodes at the precharge voltage, while the other node is pulled to a different voltage level, such as at or near a ground voltage level, wherein the node that is maintained is selected based on the state of data input signals of the level shifter. The voltage at the nodes determines the state of the level shifter output signals, such that the output signals represent the input signals at a shifted voltage level. The level shifter can include a capacitor to feed forward a signal that causes the precharging to terminate more quickly. | 02-26-2015 |
20150061097 | EDGE COUPLING OF SEMICONDUCTOR DIES - Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together. | 03-05-2015 |