Patent application number | Description | Published |
20090091487 | Spurious Free Dynamic Range Of An Analog To Digital Converter - Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved. | 04-09-2009 |
20100036460 | PARALLEL SEARCH CIRCUIT FOR A MEDICAL IMPLANT RECEIVER - Parallel search circuit for a medical implant receiver. The circuit includes a radio frequency receiver that receives a first set of contents of a band of channels. The circuit also includes a processing circuit coupled to the radio frequency receiver to process in parallel a second set of contents of a plurality of channels of the band of channels and to detect a signal in the band of channels. | 02-11-2010 |
20110006933 | TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER - A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function. | 01-13-2011 |
20110304493 | TERNARY SEARCH SAR ADC - Traditionally, successive approximation register (SAR) analog-to-digital converters (ADCs) using binary search algorithms have consumed power by performing unnecessary switching of a capacitive digital-to-analog converter (CDAC) when a CDAC voltage is relatively close to a sampling analog input signal. Here, a SAR ADC is provided that reduces the number of switching events. To accomplish this, a multi-stage comparator is provided that generates multiple output signals for SAR logic. Based on these outputs, the SAR logic can more efficiently switch its CDAC using a ternary search algorithm to reduce power consumption and improve efficiency. | 12-15-2011 |
20130294295 | TRANSMIT SIGNAL CANCELATION APPARATUS AND METHODS - Apparatus and methods disclosed herein implement an RF receive-band filter at a receive chain input of a wireless base station with a co-located transmitter and receiver. The RF receive-band filter includes an adaptive filter component to perform filtering operations on samples of a digital baseband or intermediate frequency signal x(n) from a transmit chain associated with the wireless base station. An adaptive filter transfer function is determined in real time such that samples of the baseband transmit signal x(n) are transformed into a cancellation baseband signal z(n). The digital cancelation baseband signal z(n) is then digital-to-analog converted and the resulting analog baseband signal z(t) is up-converted to obtain a subtractive RF cancelation signal c(t). C(t) is summed with a desirable received signal RF component r(t) and an undesirable transmitter leakage RF signal component l(t) appearing at the input to the base station receiver. C(t) cancels l(t), leaving r(t) to be processed by the receiver section of the base station. | 11-07-2013 |
20130307623 | Amplifier Circuits with Reduced Power Consumption - Various embodiments of an amplifier circuit are provided. In one embodiment, the amplifier circuit includes an input differential circuitry configured to convert a pair of input differential voltage signals to a pair of differential current signals. The amplifier circuit includes a cascode circuitry operable to mirror the pair of differential current signals received from the first output terminal and the second output terminal to an output terminal of the first cascode transistor and an output terminal of the second cascode transistor. The amplifier circuit includes a current control circuit operable to divert an amount of bias current to reduce a current through the cascode circuitry, to thereby reduce a load of the amplifier circuit, the reduction in the load of the amplifier circuit allowing a reduction in current through the input differential circuitry for maintaining a predetermined bandwidth of the amplifier circuit. | 11-21-2013 |
20140084982 | Circuits for Improving Linearity of Metal Oxide Semiconductor (MOS) Transistors - Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate. | 03-27-2014 |
20150077070 | FEEDFORWARD CANCELLATION OF POWER SUPPLY NOISE IN A VOLTAGE REGULATOR - A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator. | 03-19-2015 |
Patent application number | Description | Published |
20090135037 | Correcting Offset Errors Associated With A Sub-ADC In Pipeline Analog To Digital Converters - An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value). | 05-28-2009 |
20100309033 | CORRECTION OF SAMPLING MISMATCH IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals. | 12-09-2010 |
20110012764 | MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE - An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch. | 01-20-2011 |
20110102033 | LOW POWER CLOCKING SCHEME FOR A PIPELINED ADC - Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount of power. Here, a DLL is provided with a modified charge pump that allows for reduced power consumption. | 05-05-2011 |
20110102216 | APPARATUS FOR CORRECTING SETTING ERROR IN AN MDAC AMPLIFIER - Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capacitor network that compensates for this settling error. Thus, a more accurate pipelined ADC can now be produced. | 05-05-2011 |
20110204930 | SOURCE FOLLOWER INPUT BUFFER - Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved. | 08-25-2011 |
Patent application number | Description | Published |
20090058527 | Common Mode Stabilization In A Fully Differential Amplifier - A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal. | 03-05-2009 |
20090295363 | Voltage Reference With Improved Linearity Addressing Variable Impedance Characteristics At Output Node - A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation. | 12-03-2009 |
20090315594 | Source/Emitter Follower Buffer Driving a Switching Load and Having Improved Linearity - A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately. | 12-24-2009 |
20100080083 | Time-Dependant Gain Control For An Amplifier Used In Receiving Echoes - An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system. | 04-01-2010 |
20130039151 | CANCELLATION OF PRODUCTS GENERATED BY HARMONICS OF A SQUARE WAVE USED IN SQUARE-WAVE MIXING - A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square. | 02-14-2013 |