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| 20120242346 | Power Compensation in 3DIC Testing - A device, such as a 3DIC stacked device includes a first device under test (DUT) connected to a first force pad by a first through substrate via (TSV) stack and connected to a first sense pad by a second TSV stack. The device further includes a second DUT stacked above the first DUT and connected to a second force pad and a second force pad by a second third TSV and connected to a second sense pad by a fourth TSV. Functional blocks on either the first or second blocks can be accessed for testing by way of the TSVs. In some applications the TSVs are vertically aligned to form TSV stacks. | 09-27-2012 |
| 20120246514 | Adaptive Test Sequence for Testing Integrated Circuits - A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence. | 09-27-2012 |
| 20120256649 | Dynamic Testing Based on Thermal and Stress Conditions - A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results. | 10-11-2012 |
| 20120286814 | 3D IC Testing Apparatus - A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once. | 11-15-2012 |
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| 20100105270 | Fabric structure - A fabric structure includes a plurality of first light-reflecting units, a plurality of light-guiding units, and a plurality of second light-reflecting units. The cross-section of the first light-reflecting units and the second light-reflecting units is triangular or square, and the brightness of the first light-reflecting unit and the second light-reflecting units is between level | 04-29-2010 |
| 20110269358 | LUMINOUS FABRIC - A luminous fabric includes a plurality of first light-reflecting fiber units, a plurality of light-guiding fiber units, and a plurality of light-accumulating fiber units. The first light-reflecting fiber units are directed toward a first direction and spaced apart in intervals. The light-guiding fiber units are directed toward a second direction and spaced apart in intervals. Each light-guiding fiber unit has a lateral light-guiding portion. Some light-accumulating fiber units are drawn through the first light-reflecting fiber units, and some other light-accumulating fiber units are drawn through the light-guiding fiber units. Thereby, the luminous fabric can provide passive illumination when a light source is provided, and provide active illumination in dark settings. The light reflected by the luminous fabric is concentrated and uniformly distributed on one side thereof. | 11-03-2011 |
| 20120206932 | WEAVE UNIT WITH UNIFORM ILLUMINATION AND MANUFACTURING METHOD THEREOF - A weave unit includes a plurality of opaque wires; a plurality of transparent wires alternatively weaved with the opaque wires to form a weave structure, wherein a plurality of interweave points is defined on the crossing portions of the opaque wires and the transparent wires; a lighting module disposed on one side of the transparent wires; wherein the density of the interweave point on each of the transparent wires increases in the direction of being away from the lighting module; thereby, the light of the lighting module transmits inside the transparent wires for generating uniform illumination. | 08-16-2012 |
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| 20080212321 | Diffuser Having Optical Structures - A diffuser used in a backlight module including a plurality of light sources is disclosed. The diffuser according to the present invention makes a uniform light output. The diffuser includes a transparent substrate and a plurality of optical structures. The transparent substrate has an entrance surface and an exit surface. The plurality of optical structures is disposed on the exit surface, each optical structure is dented from the exit surface to the interior of the transparent substrate and forms a refractive convex within the transparent substrate, and each refractive convex corresponds to one of the plurality of the light sources. The maximum value of the included angle between the tangent to the refractive convex edge and the normal to the exit surface is smaller than 30 degrees, such that an incident light ray from the light sources refracts and deviates from the normal to the refractive convex through the refractive convex. | 09-04-2008 |
| 20090034290 | Backlight Module - A backlight module includes a light guide plate, at least one first lighting element, and at least one second lighting element. The light guide plate has a first side surface and a second side surface opposite the first side surface. The first lighting element is disposed on the first side surface and has at least three light emitting diodes of different colors. The second lighting element is disposed on the second side surface and has at least three light emitting diodes of different colors. The arrangement of the light emitting diodes of the first lighting element is different from the arrangement of the light emitting diodes of the second lighting element. | 02-05-2009 |
| 20090128741 | LCD Device, Backlight Module Thereof with Partition Wall and Method for Manufacturing the Same - A backlight module, a liquid crystal display using the backlight module, and a manufacturing method thereof are provided. The backlight module includes a bottom plate, a plurality of light source sets and at least one partition wall. A plurality of lighting areas is formed on the bottom plate and light source sets are disposed on the lighting areas, respectively. The partition wall is disposed on the bottom plate and between each two adjacent lighting areas to fully or partially block/reflect the light emitted from the lighting areas. The partition wall includes a first light-penetrable wall and a light reflective layer formed on a wall surface of first light-penetrable wall. The light reflective layer is erected on the bottom plate through the support provided by the first light-penetrable wall and its wall surface. | 05-21-2009 |
| 20110007523 | Backlight Module - This present invention discloses a backlight module including a frame and a light guide plate. The frame includes a base plane and a side wall, wherein the side wall is disposed at the edge of the base plane and encloses a disposition space. The side wall includes a first inner surface and an outer surface, wherein a distance between the first inner surface and the outer surface is decreased as the first inner surface comes closer to a bottom of the side wall. The light guide plate is disposed on the base plane and within the disposition space, wherein the first inner surface sinks toward the outer surface and a recessed space is formed between the first inner surface and a lateral side of the light guide plate. | 01-13-2011 |
| 20110058378 | Illumination Device with High Efficiency and Manufacture Method Thereof - An illumination device and a manufacture method thereof are provided. The illumination device includes a base, an illumination chip, and a sealant. The base has a surrounding side wall which encloses a containing space. The illumination chip is disposed within the containing space while the sealant fills the containing space and covers the illumination chip. The sealant has an outer surface which includes a center concave and a circular convex surrounding the center concave. The center concave is formed as a part of a spherical surface with no singular point. The connection between the center concave and the circular convex forms a circular ridge. | 03-10-2011 |
| 20110255033 | Liquid Crystal Display Device - A liquid crystal display device includes a light guide plate, a light source module, a first tape, a circuit board holder and an elastic support piece, an optical film, a panel, and an elastic buffer piece. By implement of the liquid crystal display device of this invention, the thickness and the weight of the liquid crystal display device can be reduced. | 10-20-2011 |
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| 20100219175 | ROTATABLE PLATE AND HEATING/COOLING ELEMENT IN PROXIMITY THERETO - An apparatus for selectively heating/cooling one or more substrates and establishing an approximately uniform temperature in the one or more substrates during a heating or cooling event is described. In one embodiment, the apparatus comprises a rotatable hot/cold plate onto which the one or more substrates are placed and a heating/cooling element disposed in close proximity to the rotatable hot/cold plate for selectively elevating/lowering the temperature of the one or more substrates. | 09-02-2010 |
| 20100308439 | DUAL WAVELENGTH EXPOSURE METHOD AND SYSTEM FOR SEMICONDUCTOR DEVICE MANUFACTURING - A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength. | 12-09-2010 |
| 20100321660 | METHOD AND APPARATUS FOR REDUCING DOWN TIME OF A LITHOGRAPHY SYSTEM - An apparatus includes a radiation source that emits a radiation beam that causes substantially all of a quantity of material to evaporate; and structure having first and second surface portions, a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion, and a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. A different aspect involves emitting a radiation beam toward a quantity of material, the radiation beam causing substantially all of the quantity of material to evaporate; operating a structure having first and second surface portions in a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion; and thereafter operating the structure in a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. | 12-23-2010 |
| 20120180813 | System and Method for Cleaning a Wafer Chuck - A wafer chuck is cleaned using a cleaning cap to remove processing residue and particulate matter. The cleaning cap is configured to overlie and align with the wafer chuck and includes a base and a first roller connected to the base and having wound therearound a cleaning cloth. The cleaning cap further includes a second roller connected to the base and having attached thereto a free end of the cleaning cloth. During use, the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis. The cleaning cap can be positioned relative the wafer chuck by way of a manipulator to ensure the cleaning cloth contacts the wafer chuck with sufficient force. The cleaning cloth rubs the wafer chuck with both translational motion and rotational motion. | 07-19-2012 |
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| 20090294915 | TSV-Enabled Twisted Pair - A through-silicon via (TSV) enabled twisted pair is provided. A pair of complementary conductive lines is provided as a twisted pair. Each of the conductive lines of the twisted pair is formed by alternating conductive sections on opposing sides of a substrate. The alternating conductive sections are electrically coupled by at least in part a TSV. The conductive lines overlap or are entwined such the point at which the conductive lines cross, the conductive lines are on opposing sides of the substrate. The conductive lines are weaved in this manner for the length of the conductive trace. | 12-03-2009 |
| 20110102044 | Clocking Architecture in Stacked and Bonded Dice - A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network. | 05-05-2011 |
| 20110185331 | Reducing Voltage Drops in Power Networks Using Unused Spaces in Integrated Circuits - A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added. | 07-28-2011 |
| 20120147567 | Networking Packages Based on Interposers - A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections. | 06-14-2012 |
| 20120176186 | Bandgap Reference Apparatus and Methods - Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals. | 07-12-2012 |
| 20120250286 | Apparatus and Method for Increasing Bandwidths of Stacked Dies - A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies. | 10-04-2012 |
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| 20090315743 | Increasing 8B/10B Coding Speed Using a Disparity Look-Ahead Table - A method for encoding data packets includes providing an encoding scheme for coding source data units into encoded data units; establishing a first look-ahead table for the source data units; providing a data packet including a first source data unit and a second source data unit; encoding the first source data unit to generate a first encoded data unit; indexing the first look-ahead table using the first source data unit to determine a balancing capability of the first encoded data unit for balancing a running disparity; and encoding the second source data unit to generate a second encoded data unit using the balancing capability of the first encoded data unit. | 12-24-2009 |
| 20120215497 | MEMS Modeling System and Method - A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices. | 08-23-2012 |
| 20120235208 | Semiconductor Mismatch Reduction - A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches. | 09-20-2012 |
| 20120262209 | Multi-Phase Clock Generator and Data Transmission Lines - An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals. | 10-18-2012 |
