Patent application number | Description | Published |
20080244223 | BRANCH PRUNING IN ARCHITECTURES WITH SPECULATION SUPPORT - According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation. | 10-02-2008 |
20090083488 | Enabling Speculative State Information in a Cache Coherency Protocol - In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed. | 03-26-2009 |
20100115247 | REPLACEMENT POLICY FOR HOT CODE DETECTION - Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed. | 05-06-2010 |
20100332811 | SPECULATIVE MULTI-THREADING FOR INSTRUCTION PREFETCH AND/OR TRACE PRE-BUILD - The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread. | 12-30-2010 |
20120311308 | Branch Predictor with Jump Ahead Logic to Jump Over Portions of Program Code Lacking Branches - A processor of an aspect includes front end logic to process parcels of program code. Each of the parcels has multiple instructions. A branch predictor of the processor is coupled with the front end logic. The branch predictor is to predict directions of branch instructions of the program code. The processor includes jump ahead logic to cause the branch predictor to jump over at least one parcel of the program code that does not have a branch instruction between parcels of the program code that each have at least one branch instruction. | 12-06-2012 |
20130268735 | SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA - Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state. | 10-10-2013 |
20130326199 | METHOD AND APPARATUS FOR CONTROLLING A MXCSR - Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction. | 12-05-2013 |
20130332705 | PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY - A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region. | 12-12-2013 |
20140019721 | MANAGED INSTRUCTION CACHE PREFETCHING - Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache. | 01-16-2014 |
20140095849 | INSTRUCTION AND LOGIC FOR OPTIMIZATION LEVEL AWARE BRANCH PREDICTION - A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level. | 04-03-2014 |
20140143526 | Branch Prediction Gating - In one embodiment, a processor includes at least one execution unit. The processor also includes prediction gating logic coupled to the at least one execution unit. The prediction gating logic may be to, in response to a first prediction that a first branch is taken, obtain a distance value to a second branch using a target array, and gate a branch prediction unit for a number of instruction blocks equal to the distance value to the second branch. Other embodiments are described and claimed. | 05-22-2014 |
20140156976 | METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION - Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed. | 06-05-2014 |
20140189712 | Memory Address Collision Detection Of Ordered Parallel Threads With Bloom Filters - A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads. | 07-03-2014 |