| Patent application number | Description | Published |
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| 20090273710 | IMAGE PROCESSING METHODS AND SYSTEMS FOR FRAME RATE CONVERSION - An image processing method for frame rate conversion, comprising: receiving a stream of input pictures at an input frame rate, at least some of the input pictures being new pictures, the new pictures appearing within the stream of input pictures at an underlying new picture rate; generating interpolated pictures from certain ones of the input pictures; outputting a stream of output pictures at an output frame rate, the stream of output pictures including a blend of the new pictures and the interpolated pictures, the interpolated pictures appearing in the stream of output pictures at an average interpolated picture rate; and causing a variation in the average interpolated picture rate in response to detection of a variation in the underlying new picture rate. | 11-05-2009 |
| 20090290789 | METHOD AND APPARATUS FOR REDUCED COMPLEXITY VIDEO PROCESSING VIA SPECIAL CHROMA HANDLING - A method and apparatus for reduced complexity video and image processing with special chroma handling are disclosed. Frame-type decisions are made on a video stream made up of a sequence of frames. A first subset of the frames are selected to be monochrome and generated without chroma data. A second subset of the frames are selected to be in color and generated with chroma components. In one embodiment, the first subset of frames includes odd frames and the second subset of frames includes even frames in the video stream. Under higher video frame rates, the lack of color in every other frame is not visible to the end viewer. Accordingly, subsequent processing of the output video stream permits luma-only processing of many frames in the video stream, extensively reducing the amount of computation. | 11-26-2009 |
| 20090316041 | METHOD AND APPARATUS FOR PROCESSING IMAGE DATA - A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing. | 12-24-2009 |
| 20100026888 | IMAGE PROCESSING METHOD AND SYSTEM WITH REPETITIVE PATTERN DETECTION - An image processing engine, comprising: a frame rate conversion entity configured to: (a) generate output pictures from input pictures, the output pictures comprising a set of first output pictures and a plurality of sets of second output pictures, each set of second output pictures being associated with one of the first output pictures, each of the first output pictures being derived from a respective one of the input pictures; and (b) control generation of the set of second output pictures associated with a particular first output picture based upon repetitive pattern presence detection within a related picture that is either (i) the particular first output picture or (ii) the input picture from which the particular first output picture was derived. | 02-04-2010 |
| 20100077176 | METHOD AND APPARATUS FOR IMPROVED CALCULATION OF MULTIPLE DIMENSION FAST FOURIER TRANSFORMS - Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide. | 03-25-2010 |
| 20110051005 | Method And Apparatus For Integrated Motion Compensated Noise Reduction And Frame Rate Conversion - A video processing system may receive a current raw video frame and may estimate motion between the current frame and a previous frame to determine motion vectors (mv). Based on the same mvs, motion compensated (MC) noise reduction may be performed and MC frame rate conversion (FRC) may generate a new frame. The previous frame may be noise reduced and/or a raw video frame. A MC frame may be generated based on the previous video frame and the mvs. Noise reduction may comprise blending the current raw frame with the MC frame. A blending factor may be determined based on similarity between pixels of the current video frame and MC pixels of the previous frame. The mvs may be scaled for FRC. Noise reduction may be performed in parallel and/or prior to the FRC depending on whether raw or noise reduced frames are utilized. | 03-03-2011 |
| Patent application number | Description | Published |
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| 20080231482 | METHODS AND APPARATUS FOR PROCESSING VARIABLE LENGTH CODED DATA - An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes. | 09-25-2008 |
| 20090046205 | Automatic Reduction of Video Display Device Power Consumption - One or more components of a video display device such as a television set can be powered down in response to a determination that a video input source has been paused. The video signal provided by the video input source can be analyzed to determine whether the video source is paused. When the video input source is no longer paused, the powered down components can be restored to fill power operation. | 02-19-2009 |
| 20090125702 | SIMD processor and addressing method - A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value. | 05-14-2009 |
| 20090132785 | SIMD processor executing min/max instructions - A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays. | 05-21-2009 |
| 20090175343 | HYBRID MEMORY COMPRESSION SCHEME FOR DECODER BANDWIDTH REDUCTION - A method for reducing memory bandwidth in a video decoder begins by performing a data reduction operation on a decoded first coded image to produce a second set of image data. The second set of image data stored and is selectively used for subsequent image decoding, thereby reducing the memory bandwidth. The data reduction operation can include image downsampling, wherein the pixel density is reduced by a factor of two in each of the vertical and horizontal directions. | 07-09-2009 |
| 20100013988 | METHOD AND APPARATUS FOR TRANSMITTING AND USING PICTURE DESCRIPTIVE INFORMATION IN A FRAME RATE CONVERSION PROCESSOR - A method and apparatus of frame rate conversion where descriptive information relating to an input video signal is transmitted to the frame rate converter along with the input signal. The descriptive information is used to interpolate frames, allowing the interpolator to make pixel analysis using the descriptive information relating to the original signal. The descriptive information is derived by a compositor/scaler and is transmitted to the frame rate converter with the composited/scaled signal. There may be multiple input signals that are composited to make a final composited video output such as a picture-in-picture display. The information may be transmitted in-band with the video signal received by the frame rate converter. Alternatively, the descriptive information may be transmitted in a separate stream in a side-band manner. In another embodiment, the descriptive information may be transmitted to the frame rate converter separate from the video input source as commands or packets. | 01-21-2010 |
