Patent application number | Description | Published |
20080209187 | Storing and processing SIMD saturation history flags and data size - A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturation operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation. | 08-28-2008 |
20080270768 | Method and apparatus for SIMD complex Arithmetic - Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand. | 10-30-2008 |
20090300325 | DATA PROCESSING SYSTEM, APPARATUS AND METHOD FOR PERFORMING FRACTIONAL MULTIPLY OPERATIONS - A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core. | 12-03-2009 |
20100185821 | Local cache power control within a multiprocessor system - A data processing system including a plurality of processors | 07-22-2010 |
20120057801 | Residual Addition for Video Software Techniques - According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results. | 03-08-2012 |
Patent application number | Description | Published |
20090150620 | Controlling cleaning of data values within a hardware accelerator - A data processing apparatus | 06-11-2009 |
20090172329 | Providing secure services to a non-secure application - A data processing apparatus comprising a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor processing data in said non-secure mode; and a further processing device for performing a task in response to a request from said data processor issued from said non-secure mode, said task comprising processing data at least some of which is secure data, said further processing device comprising a secure data store, said secure data store not being accessible to processes running on said data processor in non-secure mode; wherein prior to issuing any of said requests said data processor is adapted to perform a set up operation on said further data processing device, said set up operation being performed by said data processor operating in said secure mode and comprising storing secure data in said secure data store on said further processing device, said secure data being secure data required by said further processing device to perform said task; wherein in response to receipt of said request from said data processor operating in said non-secure mode said further data processing device performs said task using data stored in said secure data store to access any secure data required. | 07-02-2009 |
20090172411 | Protecting the security of secure data sent from a central processor for processing by a further processing device - A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode. | 07-02-2009 |
20090216958 | Hardware accelerator interface - A data processing system in the form of an integrated circuit | 08-27-2009 |
20090265514 | Efficiency of cache memory operations - A processing system | 10-22-2009 |
20110307664 | Cache device for coupling to a memory device and a method of operation of such a cache device - A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilisation, thereby giving rise to both performance improvements and power consumption reductions. | 12-15-2011 |
20130036270 | Data processing apparatus and method for powering down a cache - A data processing apparatus is provided comprising a processing device, and an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data. Dirty way indication circuitry is configured to generate an indication of the degree of dirty data stored in each way. Further, staged way power down circuitry is responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data. This approach provides a particularly quick and power efficient technique for powering down the cache in a plurality of stages. | 02-07-2013 |