Patent application number | Description | Published |
20140025223 | Performance Management of Subsystems in a Server by Effective Usage of Resources - An approach is provided in which a subsystem cooling manager detects an increased workload indicator corresponding to a computer subsystem's forthcoming workload requirement. The forthcoming workload requirement corresponds to future computing resources required by the subsystem to support one or more software programs executing on the computer system. The subsystem cooling manager determines that the forthcoming workload requirement exceeds a utilization threshold and in turn, directs one or more cooling systems towards the corresponding subsystem according. | 01-23-2014 |
20140053016 | Using A Buffer To Replace Failed Memory Cells In A Memory Component - Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component. | 02-20-2014 |
20140063987 | MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES - A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices. | 03-06-2014 |
20140164819 | MEMORY OPERATION OF PAIRED MEMORY DEVICES - A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. | 06-12-2014 |
20140164853 | MEMORY OPERATION OF PAIRED MEMORY DEVICES - A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices. | 06-12-2014 |
20140188409 | DETECTING TSV DEFECTS IN 3D PACKAGING - A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect. | 07-03-2014 |
20140355369 | MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES - A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices. | 12-04-2014 |
Patent application number | Description | Published |
20130138901 | IIMPLEMENTING MEMORY PERFORMANCE MANAGEMENT AND ENHANCED MEMORY RELIABILITY ACCOUNTING FOR THERMAL CONDITIONS - A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory. | 05-30-2013 |
20140281681 | ERROR CORRECTION FOR MEMORY SYSTEMS - According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark. | 09-18-2014 |
20150205730 | IMPLEMENTING ENHANCED SECURITY WITH STORING DATA IN DRAMs - A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register. | 07-23-2015 |
20150205731 | IMPLEMENTING ENHANCED SECURITY WITH STORING DATA IN DRAMs - A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register. | 07-23-2015 |
20150268857 | SYSTEM AND METHOD FOR COMPUTER MEMORY WITH LINKED PATHS - A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer. | 09-24-2015 |
20150269096 | SYSTEM AND METHOD FOR COMPUTER MEMORY WITH LINKED PATHS - A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer. | 09-24-2015 |
20150279433 | ALLOCATING MEMORY ADDRESS SPACE BETWEEN DIMMS USING MEMORY CONTROLLERS - A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. | 10-01-2015 |
20150279461 | ALLOCATING MEMORY ADDRESS SPACE BETWEEN DIMMS USING MEMORY CONTROLLERS - A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. | 10-01-2015 |